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參數(shù)資料
| 型號(hào)： | MT9V011 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR |
| 中文描述： | 4英寸顯卡的CMOS有源像素的數(shù)字圖像傳感器 |
| 文件頁數(shù)： | 17/33頁 |
| 文件大小： | 537K |
| 代理商： | MT9V011 |
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1/4-INCH VGA CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Preliminary
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
17
2004 Micron Technology, Inc.
Register Descriptions
Table 7:
Register Description
REGISTER
BIT
DESCRIPTION
Chip Version
0x00 / 0xFF
Window Control
These registers control the size of the window.
0x01
0-8
First row to be read out
—
default = 0x000A (10).
Minimum recommended value = 0x0006.
0x02
0-9
First column to be read out
—
default = 0x0016 (22). Minimum recommended value = 0x0012 (18).
0x03
0-8
Window height (number of rows - 1)
—
default = 0x01DF (479).
0x04
0-9
Window width (number of columns - 1)
—
default = 0x027F (639).
Minimum recommended value = 0x0009.
Blanking Control
These registers control the blanking time in a row and between frames.
0x05
0-9
Horizontal Blanking (number of columns)
—
default = 0x0083 (131 pixel clocks).
Minimum value for 0x05 = 0x0009.
Minimum recommended value for 0x05 = 0x007B (123 pixel clocks).
0x06
0-11
Vertical Blanking (number of rows -1)
—
default = 0x001C (28 rows).
Minimum recommended value = 0x0003.
Output Control
This register controls various features of the output format for the sensor.
0x07
0
Synchronize changes (copied to Reg0xF1, bit1).
0 = normal operation, update changes to registers that affect image brightness (integration time,
integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row
mirror) at the next frame boundary.
1 = do not update any changes to these settings until this bit is returned to “0.”
1
Chip Enable (copied to Reg0xF1, bit0).
1 = normal operation.
0 = stop sensor readout. When this is returned to “1,” sensor readout restarts at the starting row in a
new frame. The digital power consumption can then also be reduced to less than 5uA by turning off
the master clock.
4
By setting this bit to “1,” the sampling and reset timing of the pixels will be halved. This bit should
therefore only be used if the master clock frequency is 13.5 MHz or less. When this bit is set the
minimum recommended horizontal blanking value is 17, compared to 123 when this bit is not set.
Shutter Delay will be master clocks divided by 2 when this bit is set, compared to master clocks
divided by 4 when this bit is 0.
Note: Use this register for 15 fps with 12 MHz master clock.
5
Allow Shutter Width to be exactly one full frame.
0 = normal operation = Maximum Shutter Width equals the total number of rows - 1. If Shutter
Width exceeds the number of rows -1, the total number of rows in the image will be increased to
Shutter Width + 1.
1 = Maximum Shutter Width equals the total number of rows. When the Shutter Width exceeds the
number of rows, the total number of rows in the image will be increased to match the Shutter Width.
6
Reserved.
8 -11
Shift pixel clock: (11,10,9,8) = (1, x, x, x): shift pixel clock 1 clock earlier (0, 1, x, x): shift pixel clock
clock earlier (0, 0, 1, x): delay pixel clock by clock(0, 0, 0, 1): delay pixel clock by 1 clock (0, 0, 0, 0):
no delay pixel clock (default mode).
15
Invert pixel clock:
0 = normal operation.
1 = invert pixel clock.
0-15
This register is read-only and gives the chip identification number: 0x8232.
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