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參數(shù)資料
| 型號(hào)： | MT9V011 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR |
| 中文描述： | 4英寸顯卡的CMOS有源像素的數(shù)字圖像傳感器 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 537K |
| 代理商： | MT9V011 |
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1/4-INCH VGA CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Preliminary
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
2004 Micron Technology, Inc.
Serial Bus Description
Registers are written to and read from the MT9V011
through the two-wire serial interface bus. The sensor is
a serial interface slave and is controlled by the serial
clock (SCLK), which is driven by the serial interface
master. Data is transferred into and out through the
MT9V011 serial data (SDATA) line. The SDATA line is
pulled up to V
DD
off-chip by a 1.5K
resistor. Either
the slave or master device can pull the SDATA line
down—the serial interface protocol determines which
device is allowed to pull the SDATA line down at any
given time. The registers are 16 bits wide, and can be
accessed through 16- or eight-bit two-wire serial bus
sequences.
Protocol
The two-wire serial interface defines several differ-
ent transmission codes, as follows:
a start bit
the slave device eight-bit address
a(n) (no) acknowledge bit
an eight-bit message
a stop bit
Sequence
A typical read or write sequence begins by the mas-
ter sending a start bit. After the start bit, the master
sends the slave device’s eight-bit address. The last bit
of the address determines if the request will be a read
or a write, where a “0” indicates a write and a “1” indi-
cates a read. The slave device acknowledges its address
by sending an acknowledge bit back to the master.
If the request was a write, the master then transfers
the eight-bit register address to which a write should
take place. The slave sends an acknowledge bit to indi-
cate that the register address has been received. The
master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight
bits. The MT9V011 uses 16-bit data for its internal reg-
isters, thus requiring two eight-bit transfers to write to
one register. After 16 bits are transferred, the register
address is automatically incremented, so that the next
16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
A typical read sequence is executed as follows. First
the master sends the write-mode slave address and
eight-bit register address, just as in the write request.
The master then sends a start bit and the read-mode
slave address. The master then clocks out the register
data eight bits at a time. The master sends an acknowl-
edge bit after each eight-bit transfer. The register
address is auto-incremented after every 16 bits is
transferred. The data transfer is stopped when the
master sends a no-acknowledge bit. The MT9V011
allows for eight-bit data transfers through the two-wire
serial interface by writing (or reading) the most signifi-
cant eight bits to the register and then writing (or read-
ing) the least significant eight bits to Reg0x80 (128).
Bus Idle State
The bus is idle when both the data and clock lines
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition
of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition
of the data line while the clock line is HIGH.
Slave Address
The eight-bit address of a two-wire serial interface
device consists of seven bits of address and 1 bit of
direction. A “0” in the LSB of the address indicates
write mode, and a “1” indicates read mode. The write
address of the sensor is 0xBA, while the read address is
0xBB.
Data Bit Transfer
One data bit is transferred during each clock pulse.
The two-wire serial interface clock pulse is provided by
the master. The data must be stable during the HIGH
period of the serial clock—it can only change when the
two-wire serial interface clock is LOW. Data is trans-
ferred eight bits at a time, followed by an acknowledge
bit.
Acknowledge Bit
The master generates the acknowledge clock pulse.
The transmitter (which is the master when writing, or
the slave when reading) releases the data line, and the
receiver indicates an acknowledge bit by pulling the
data line low during the acknowledge clock pulse.
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| MT9V011P11ST | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR |
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