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參數(shù)資料
| 型號： | MT93L16 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| 中文描述： | 低電壓聲回波消除器（低電壓回聲消除器） |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 118K |
| 代理商： | MT93L16 |
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Preliminary Information
MT93L16
3
Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.
2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers
on a shared bus).
Glossary
Double-Talk
Simultaneous signals present on Rin and Sin.
Near-end Single-Talk
Signals only present at Sin input.
Far-end Single-Talk
Signals only present at Rin input.
ADV NLP
Advanced Non-Linear-Processor
Howling
Oscillation caused by feedback from acoustic and line echo paths
Narrowband
Any mono or dual sinusoidal signals
NBSD
Narrow Band Signal Detector
Noise-Gating
Audible switching of background noise
Offset Nulling
Removal of DC component
Reverberation time
The time duration before an echo level decays to -60dBm
ERL
Echo Return Loss
ERLE
Echo Return Loss Enhancement
AGC
Automatic Gain Control
14
RESET
Reset / Power-down (Input).
An active low resets the device and puts the MT93L16 into a
low-power stand-by mode.
15, 16
NC
No Connect (Output).
These pins should be left un-connected.
17
SCLK
Serial Port Synchronous Clock (Input).
Data clock for the serial microport interface.
18
CS
Serial Port Chip Select (Input).
Enables serial microport interface data transfers. Active low.
19
DATA2
Serial Data Receive (Input).
In Motorola/National serial microport operation, the DATA2 pin
is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and
must be tied to Vss or Vdd.
20
DATA1
Serial Data Port (Bidirectional).
In Motorola/National serial microport operation, the DATA1
pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for
transmitting and receiving data.
21
NC
No Connect (Output).
This pin should be left un-connected.
22
VDD
Positive Power Supply (Input)
. Nominally 3.3 volts.
23
Sout
Send PCM Signal Output (Output).
128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. This is the Send
Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked
out following SSI, ST-BUS, or GCI timing requirements.
24
Rout
Receive PCM Signal Output (Output).
128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. This is the Receive
out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits
are clocked out following SSI, ST-BUS, or GCI timing requirements.
25
F0i
Frame Pulse (Input).
In ST-BUS (or GCI) operation, this is an active-low (or active-high)
frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.
26
BCLK/C4i
Bit Clock/ST-BUS Clock (Input)
. In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit
clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.
27, 28
IC
Internal Connection (Input).
Tie to Vss.
29
VSS2
Digital Ground (Input):
Nominally 0 volts.
30
VDD2
Positive Power Supply (Input)
: Nominally 3.3 volts (tie together with VDD, pin 22).
31
VSS
Digital Ground (Input):
Nominally 0 volts (tie together with VSS2, pin 29).
32
NC
No Connect (Output).
This pin should be left un-connected.
33
MCLK2
Master Clock (Input):
Nominal 20MHz master clock (tie together with MCLK, pin 8).
34,35,36
IC
Internal Connection (Input).
Tie to Vss.
Pin Description (continued)
Pin #
Name
Description
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