
MT93L16
Preliminary Information
2
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
ENA1
SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input)
. This pin has dual functions
depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present
for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits
wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125
microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the
proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description).
2
MD1
ST-BUS & GCI Mode for Rin/Sout (Input)
. When in ST-BUS or GCI operation, this pin, in
conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS
and GCI Operation description). Connect this pin to Vss in SSI mode.
3
ENA2
SSI Enable Strobe / ST-BUS & GCI Mode for Sin/Rout (Input)
.This pin has dual functions
depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins.
Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2
pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description).
4
MD2
ST-BUS & GCI Mode for Sin/Rout (Input)
.When in ST-BUS or GCI operation, this pin in
conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and
GCI Operation description). Connect this pin to Vss in SSI mode.
5
Rin
Receive PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2’s complement linear format. This is the Receive Input
channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-
BUS timing requirements.
6
Sin
Send PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2’s complement linear format. This is the Send Input channel
(from the microphone). Data bits are clocked in following SSI,GCI or ST-BUS timing
requirements.
7
IC
Internal Connection (Input):
Must be tied to Vss.
8
MCLK
Master Clock (Input):
Nominal 20 MHz Master Clock input (may be asynchronous relative
to 8KHz frame signal.) Tie together with MCLK2 (pin 33).
9,10,11
IC
Internal Connection (Input):
Must be tied to Vss.
12
LAW
A/
μ
Law Select (Input).
When low, selects
μ
Law companded PCM. When high, selects A-
Law companded PCM. This control is for both serial pcm ports.
13
FORMAT
ITU-T/Sign Mag (Input).
When low, selects sign-magnitude PCM code. When high, selects
ITU-T (G.711) PCM code. This control is for both serial pcm ports.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
28
27
26
25
24
23
22
20
DATA2
VDD
NC
DATA1
IC
IC
IC
NC
SCLK
CS
Sout
BCLK/C4i
F0i
IC
IC
Sin
IC
Rin
MD1
ENA2
FORMAT
RENC
LAW
ENA1
MCLK
QSOP
32
31
30
29
VSS
NC
VDD2
33
34
35
MCLK2
IC
IC
IC