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參數(shù)資料
| 型號： | MT93L16 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| 中文描述： | 低電壓聲回波消除器（低電壓回聲消除器） |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 118K |
| 代理商： | MT93L16 |
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Preliminary Information
MT93L16
11
writes. Resetting the bootload bit (
C
2
) in the BRC
register to 0 (see Register Summary) exits bootload
mode, resetting the signature (SIG) register and
internal address generator for the next bootload. A
hardware reset (RESET=0) similarly returns the
MT93L16 to the ready state for the start of a
bootload.
Once the program has been loaded, to begin
execution from RAM, bootload mode must be
disabled (BOOT bit,
C
2
=0) and execution from RAM
enabled (RAM_ROMb bit,
C
3
=1) by setting the
appropriate bits in the BRC register. During the
bootload process, however, ROM program execution
(RAM_ROMb bit,
C
3
=0) should be selected. See
Table 5 for the effect of the BRC register settings on
Microport accesses and on program execution.
Following program loading and enabling of execution
from RAM, it is recommended that users set the
software reset bit in the Main Control (MC) register,
to ensure that the device updates the default register
values to those of the new program in RAM. Note: it
is important to use a software reset rather than a
hardware (RESET=0) reset, as the latter will return
the device to its default settings (which includes
execution from program ROM instead of RAM.)
To verify which code revision is currently running,
users can access the Firmware Revision Code
(FRC) register (see Register Summary). This
register reflects the identity code (revision number)
of the last program to run register initialization (which
follows a software or hardware reset.)
Table 5 - Bootload RAM Control (BRC) Register States
Note: bits C
1
C
0
are reserved, and must be set to zero.
FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)
BRC Register
Bits
C
3
C
2
C
1
C
0
X 1 0 0
R/W
Address
Data
W
3fh
(= 1 1 1 1 1 1 b)
Writes "data" to BRC reg.
- Bootload frozen; BRAM contents are NOT affected.
W
other than 3fh
Writes "data" to next byte in BRAM (bootloading.)
R
1 x x x x x b
Reads back "data" = BRC reg value.
- Bootload frozen; BRAM contents are NOT affected.
R
0 x x x x x b
Reads back "data" = SIG reg value.
- Bootload frozen; BRAM contents are NOT affected.
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)
BRC Register
Bits
C
3
C
2
C
1
C
0
X 0 0 0
R/W
Address
Data
W
any
a
3
a
2
a
1
a
0
b)
(=
a
5
a
4
Writes "data" to corresponding DREG.
R
any
a
3
a
2
a
1
a
0
b)
(=
a
5
a
4
Reads back "data" = corresponding DREG value.
PROGRAM EXECUTION MODES
C
C
C
C
0
0 0 0 0
Execute program in ROM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C
3
C
2
C
1
C
0
0 1 0 0
Execute program in ROM, while bootloading the RAM.
- BRAM address counter increments on microport writes (except to 3fh)
- SIG reg recalculates signature on microport writes (except to 3fh)
C
3
C
2
C
1
C
0
1 0 0 0
Execute program in RAM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C
3
C
2
C
1
C
0
1 1 0 0
- NOT RECOMMENDED -
(Execute program in RAM, while bootloading the RAM)
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