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Data Sheet
MT90869
7
Zarlink Semiconductor Inc.
TMS
D12
Test Mode Select (5V Tolerant with internal pull-up).
JTAG signal that controls
the state transitions of the TAP controller.
TCK
A14
Test Clock (5V Tolerant).
Provides the clock to the JTAG test logic.
TDi
B13
Test Serial Data In (5V Tolerant with internal pull-up).
JTAG serial test
instructions and data are shifted in on this pin.
TDo
C13
Test Serial Data Out (5V Tolerant Three-state Output).
JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG is not enabled.
TRST
B14
Test Reset (5V Tolerant with internal pull-up)
Asynchronously initializes the
JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low during power-
up for JTAG testing. This pin must be held LOW for normal functional operation of
the device.
RESET
C12
Device Reset (5V Tolerant with internal pull-up).
This input (active LOW)
asynchronously applies reset and synchronously releases reset to the device. In
the reset state, the outputs LSTo0 - 31 and BSTo0 - 31 are set to a high or high
impedance depending on the state of the LORS and BORS external control pins,
respectively. It clears the device registers and internal counters. This pin must stay
low for more than 2 cycles of input clock C8i for the reset to be invoked.
LSTi0-31
L18, L19, L20, M17,
M18,
M19, M20, N18,
N19, N20, P17, P19,
P20, R18, R19, R20,
T18, T19, T20, U18,
U19, U20, V17, V18,
V19, V20, W18,
W19, Y20, Y17, Y18,
Y19
Local Serial Input Streams 0 to 31 (5V Tolerant with internal pull-down).
These pins accept serial TDM data streams at a data-rate of:-
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o
W13
C16o Output Clock (Three-state Output).
A 16.384MHz clock output. The clock
falling edge or rising edge is aligned with the local frame boundary, this is
controlled by the COPOL bit of the Control Register.
C8o
V13
C8o Output Clock (Three-state Output).
A 8.192MHz clock output. The clock
falling edge or rising edge is aligned with the local frame boundary, this is
controlled by the COPOL bit of the Control Register.
FP16o
W14
Frame Pulse Output (Three-state Output).
Frame pulse output is active for 61ns
at the frame boundary. The frame pulse, running at a 8KHz rate, will be the same
format (ST-BUS or GCI-BUS) as the input frame pulse (FP8i).
FP8o
V14
Frame Pulse Output (Three-state Output).
Frame pulse output is active for
122ns at the frame boundary. The frame pulse, running at 8KHz rate, will be the
same style (ST-BUS or GCI-BUS) as the input frame pulse (FP8i).
LSTo0 - 31
A17, A18, A19, B18,
B19, B20, C18, C19,
C20, D18, D19, D20,
E17, E18, E19, E20,
F18, F19, F20, G17,
G18, G19, G20,
H18, H19, H20, J17,
J18, J19, J20, K17,
K18
Local Serial Output Streams 0 to 31 (5V Tolerant Three-state Outputs).
These
pins output serial TDM data streams at a data-rate of:-
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
Refer to descriptions of the
LORS
and
ODE
pins for control of the output High or
High-Impedance state.
Pin Description (continued)
Name
Package
Coordinates
Description