參數(shù)資料
型號: MT90869
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: 靈活的16K的數(shù)字交換機(jī)(F16kDX)
文件頁數(shù): 23/76頁
文件大?。?/td> 1316K
代理商: MT90869
Data Sheet
MT90869
23
Zarlink Semiconductor Inc.
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus mode)
4.2
Backplane High Impedance Control
The input pin,
BORS
, selects whether the Backplane output streams,
BSTo0-31
are set to high impedance at the
output of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if
required on a per-channel basis, is invoked through an external interface circuit controlled by the
BCSTo0-3
signals. Setting
BORS
to a LOW state will configure the output streams,
BSTo0-31,
to transmit bi-state channel
data with per-channel high-impedance determined by external circuits under the control of the
BCSTo0-3
outputs.
Setting
BORS
to a HIGH state will configure the output streams,
BSTo0-31,
of the MT90869 to invoke a high-
impedance output on a per-channel basis.
The state of the
BORS
pin is detected and the MT90869 configured accordingly during a
RESET
operation, e.g.
following power-up. The BORS pin is an asynchronous input and is expected
to be hard-wired for a particular
system application, although it may be driven under logic control if preferred.
Chan 0 Bit 7
Chan 0 Bit 6
Chan 63 Bit 1
Chan 63 Bit 0
Chan 0
Bit 7
Chan 63
Bit 0
7
6
5
4
3
2
3
2
1
0
5
4
1
6
0
7
7
6
0
Chan 0
Bit 7
Chan 0
Bit 6
Chan 0
Bit 5
Chan 0
Bit 4
Chan 127
Bit 3
Chan 127
Bit 2
Chan 127
Bit 1
Chan 127
Bit 0
Chan 0
Bit 7
Chan 127
Bit 0
Channel 0 Bit 7
Channel 31 Bit 0
Chan 0
Bit 7
Chan 31
Bit 0
LCSTo0
LSTo0
(16Mb/s)
LSTo1
(8Mb/s)
LSTo6
(4Mb/s)
LSTo7
(2Mb/s)
C8o
FP8o
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LCSTo1
LCSTo2
LCSTo3
One C16o period
Channel 0
Channel 255 bits 7-0
C
L
1
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