參數(shù)資料
型號(hào): MT9075B
廠商: Mitel Networks Corporation
英文描述: E1 Single Chip Transceiver
中文描述: 素E1單芯片收發(fā)器
文件頁(yè)數(shù): 40/78頁(yè)
文件大小: 347K
代理商: MT9075B
MT9075B
Preliminary Information
40
Bit
Name
Functional Description
7-3
--
Unused.
2
LOS/LOF
(0)
Loss of Signal or Loss of Frame
Selection.
If one, pin LOS (pin 61 in
PLCC, 57 in MQFP) will go high
when a loss of signal state exits
(criteria as per LLOS status bit on
page 03H address 18H). If low, pin
LOS will go high when either a loss
of signal (LLOST =1) or a loss of
basic frame alignment state exits
(bit SYNC on page 03H address
10H is zero).
1
ADSEQ
(0)
Digital Milliwatt or Digital Test
Sequence.
If one, the A-law digital
milliwatt analog test sequence will
be selected by the Per Time Slot
Control bits TTST and RTST (on
page 07H and 08H). If zero, the
PRBS 2
15
-1 bit error rate test
sequence will be selected by the
Per Time Slot Control bits TTST and
RTST. The PRBS generator is reset
whenever this bit is set to 1.
0
GCI/ST
(0)
GCI or ST-BUS Frame Pulse.
If
one, the MT9075B will transmit or
receive a GCI frame pulse on pin
F0b (pin 46 in PLCC, 34 in MQFP).
If zero, the MT9075B will transmit or
receive an ST-BUS frame pulse on
F0b.
Table 29 - Access Control Word
(Page 02H, Address 13H)
Bit
Name
Functional Description
7
JAS
(0)
Jitter Attenuator Select.
If one,
the attenuator may be connected to
either the transmit or receive sides
of the PCM 30 interface depend on
bit 6 - JAT/JAR. If zero, the jitter
attenuator function is disabled.
6
JAT/JAR
(0)
Transmit
Attenuator.
If one, the jitter
attenuator will function on the
transmit data. If zero, the jitter
attenuator will function on the
receive data.
or
Receive
Jitter
5
JFC
(0)
Jitter Attenuator FIFO Centre.
When this bit is toggled the read
pointer of the jitter attenuator shall
be centered. During centering the
jitter in the JA outputs is increased
by 0.0625 U.I
4 - 2
JFD2-
JFD0
(00)
Jitter Attenuator FIFO Depth
Control Bits.
These bits determine
the depth of the jitter attenuator
FIFO as shown below:
JFD2
JFD1
JFD0
Depth
(words)
0
0
0
16
0
0
1
32
0
1
0
48
0
1
1
64
1
0
0
80
1
0
1
96
1
1
0
112
1
1
1
128
1
JACL
(0)
Jitter Attenuator Clear bit.
If one,
the Jitter Attenuator, its FIFO and
status are reset. The status
registers will identify the FIFO as
being empty. However, the actual
bit values of the data in the JA
FIFO will not be reset.
0
---
Unused.
Table 30 - Jitter Attenuator Control Word
(Page 02H, Address 18H)
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