參數(shù)資料
型號(hào)： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁(yè)數(shù)： 43/122頁(yè)
文件大?。?/td> 372K
代理商： MT9074
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Advance Information
MT9074
43
Bit
Name
Functional Description
7
ESF
Extended
Setting
transmission and reception of
the 24 frame superframe DS1
protocol.
Super
this
Frame
.
enables
bit
6
SLC96
SLC96 Mode Select
. Setting
this bit enables input and output
of the Fs bit pattern on the TxDL
and
RxDL
synchronization is the same as
in the case of D4 operation. The
transmitter will insert A and B
bits every 6 frames after
synchronizing to the Fs pattern
clocked into Txdl. Receive Fs
bits are not monitored for the
Framing Bit Error Counter.
pins.
Frame
5
CXC
Cross Check
. Setting this bit in
ESF mode enables a cross
check of the CRC-6 remainder
before the frame synchronizer
pulls into sync. This process
adds at least 6 milliseconds to
the frame synchronization time.
Setting this bit in D4 (not ESF)
mode enables a check of the Fs
bits in addition to the Ft bits
during frame synchronization
4 - 3
RS1- 0
Reframe Select 1 - 0
. These
bits set the criteria for an
automatic reframe in the event
of framing bits errors. The
combinations available are:
RS1 - 0, RS0 - 0 = sliding
window of 2 errors out of 4.
RS1 - 0, RS0 - 1 = sliding
window of 2 errors out of 5.
RS1 - 1, RS0 - 0 = sliding
window of 2 errors out of 6.
RS1 - 1, RS0 - 1 = no reframes
due to framing bit errors.
Table 21 - Framing Mode Select (T1)
(Page 1, Address 10H)
2
FSI
Fs Bit Include
. Only applicable
in D4 mode (not ESF or
SLC96). Setting this bit causes
errored Fs bits to be included as
framing bit errors. A bad Fs bit
will increment the Framing Error
Bit Counter, and will potentially
cause a reframe (if it is the
second bad framing bit out of 5).
The Fs bit of the receive frame
12 will only be included if
D4SECY is set low.
1
ReFR
Reframe
. Setting this bit causes
an automatic reframe.
0
MFReFR
MultiFrame
applicable in D4 or SLC96
mode. Setting this bit causes an
automatic multiframe reframe.
The signalling bits are frozen
until multiframe synchronization
is achieved. Terminal frame
synchronization is not affected.
Reframe
.
Only
Bit
Name
Functional Description
Table 21 - Framing Mode Select (T1)
(Page 1, Address 10H)
相關(guān)PDF資料
PDF描述
MT9074AL T1/E1/J1 Single Chip Transceiver
MT9074AP T1/E1/J1 Single Chip Transceiver
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074AL 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
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