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參數(shù)資料
| 型號(hào)： | MT9072 |
| 廠商： | Zarlink Semiconductor Inc. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 73/275頁(yè) |
| 文件大?。?/td> | 3738K |
| 代理商： | MT9072 |
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MT9072
Data Sheet
73
Zarlink Semiconductor Inc.
9.1 HDLC Description
The HDLC handles the bit oriented protocol structure as per layer 2 of the switching protocol X.25 defined by
CCITT. It transmits and receives the packetized data serially while providing data transparency by zero insertion
and deletion. It generates and detects the flags, various link channel states and abort sequences. Further, it
provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it can
recognize a single byte, dual byte and all call address in the received frame. Access to Rx CRC and inhibiting of Tx
CRC for terminal adaptation is also provided. The HDLC controller has two 32 byte deep FIFO’s associated with it;
one for Transmit and one for Receive.
9.1.1 HDLC Frame Structure
A valid HDLC frame begins with an opening flag, contains at least 16 bits of address and control or information, and
ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner is also referred to as a “packet”.
Refer to Table 33.
All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags and
appends them to the packet to be transmitted. The receiver searches the incoming data stream for the flags on a
bit- by-bit basis to establish frame synchronization.
The data field consists of an address field, control field and information field. The address field consists of one or
two bytes directly following the opening flag. The control field consists of one byte directly following the address
field. The information field immediately follows the control field and consists of N bytes of data. The HDLC does not
distinguish between the control and information fields and a packet does not need to contain an information field to
be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CRC-CCITT standard generator polynomial “X
16
+X
12
+X
5
+1” produces the 16-bit FCS. In the transmitter the FCS is
calculated on all bits of the address and data field. The complement of the FCS is transmitted, most significant bit
first, in the FCS field. The receiver calculates the FCS on the incoming packet address, data and FCS field and
compares the result to “F0B8”. If no transmission errors are detected and the packet between the flags is at least 32
bits in length then the address and data are entered into the receive FIFO minus the FCS which is discarded.
9.1.2 Data Transparency (Zero Insertion/Deletion)
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of 5 contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
9.1.3 Invalid Frames
A frame is invalid if one of the following four conditions exists (Inserted zeros are not part of a valid count):
If the FCS pattern generated from the received data does not match the “F0B8” pattern then the last data
byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the receiver
and nothing is written to the receive FIFO.
Flag (7E)
Data Field
FCS
Flag (7E)
One Byte
01111110
n Bytes
n
≥
2
Two Bytes
One Byte
01111110
Table 33 - HDLC Frame Format
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
| MT90820AL | Large Digital Switch |
| MT90820AL1 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
| MT9072AV2 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays |
| MT90732 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
| MT90732AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
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