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MT9072
Data Sheet
201
Zarlink Semiconductor Inc.
4
CEFSI
Consecutively Errored Frame Alignment Signal Interrupt.
This bit is one when the
corresponding latched status bit (CEFSL, register address Y24) is set, and the corresponding
mask bit is unmasked (CEFSM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
3
RFAILI
Remote CRC-4 Multiframe Generator/Detector Failure Interrupt.
This bit is one when the
corresponding latched status bit (RFAILL, register address Y24) is set, and the corresponding
mask bit is unmasked (RFAILM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
2
CSYNCI
Receive CRC-4 Synchronization Interrupt.
This bit is one when the corresponding latched
status bit (CSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (CSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
1
MSYNCI
Receive Multiframe Alignment Interrupt.
This bit is one when the corresponding latched
status bit (MSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (MSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
0
BSYNCI
Receive Basic Frame Alignment Interrupt.
This bit is one when the corresponding latched
status bit (BSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (BSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
Bit
Name
Functional Description
15
#
not used.
14
SLOI
Loss of Sync Counter Overflow Interrupt.
This bit is one when the corresponding latched
status bit (SLOL, register address Y25) is set, and the corresponding mask bit is unmasked
(SLOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
13
FEOI
Frame Alignment Signal (FAS) Error Counter Overflow Interrupt.
This bit is one when the
corresponding latched status bit (FEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (FEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
12
FEII
Frame Alignment Signal (FAS) Error Counter Indication Interrupt.
This bit is one when
the corresponding latched status bit (FEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (FEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
11
BEOI
Frame Alignment Signal (FAS) Bit Error Counter Overflow Interrupt.
This bit is one when
the corresponding latched status bit (BEOL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEOM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
Table 179 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)
Bit
Name
Functional Description
Table 178 - Sync, CRC-4 Remote, Alarms, MAS and Phase Interrupt Status Register (Address Y34) (E1)