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參數(shù)資料
| 型號(hào)： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁(yè)數(shù)： | 45/233頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
45
Zarlink Semiconductor Inc.
4.2.4.2 CAS Operation
Figure 11 - TDM Channel Association: TX Channels (CAS mode)
The RX Byte Write bits remain the same to allow the insertion of null patterns as for regular channels. The Mode
bits, indicate the possible configurations and combinations of multiframing and CAS insertion: “0100” is E1, “0110”
is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of transmitting the
data and CAS bytes is being used. FASTCAS is used to lower the latency of Circuit Emulation cells. When using
the FASTCAS mode, the multiframe pointer is not used and multiframe integrity is therefore not maintained.
In addition, special fields for CAS are added in the two additional words of the structure. The CAS WE (CAS Write
Enable) bits are used to determine if the CAS is written back.
The TX_CAS field is used so the CPU can insert values of CAS, in place of values from the TDM bus; the RX CAS
value is used to compensate for underruns.
The Last TX CAS field is used to detect when the CAS value received on the TDM bus has changed. When a CAS
value is received, it is written back to the Last TX CAS field in the structure. Whenever a new value arrives, it is
compared to the last value. If there is a difference, a CAS change signal is sent to the registers, and the new CAS
value is written to the CAS change buffer in the external memory.
The Frame Offset field is used to store the offset between the internal and external multiframes in the TX direction.
When the TDM bus first obtains an external multiframe, it writes the offset field to the correct value between 0 and
b8
b9
b10
b11
b12
TX/RX Circular Buffer Address and Size
b13
b14
b15
+0
b0
I
b1
b2
b3
b4
b5
b6
b7
+2
1
Reserved
Mode
TX/RX Circular Buffer Address and Size
: Address and size of the circular buffer in the data memory
to which data bytes will be written.
I
: Initialized Bit. Written by ‘0’ by software, set by hardware when the channel starts being treated.
Mode
: Channel Mode of operation.
“0100”=E1 Strict Multiframing;
“0101”=E1 FASTCAS;
“0110”=T1 Strict Multiframing;
“0111”=T1 FASTCAS;
others=Reserved.
RBW
: RX Byte Write. Selects byte that will be written in the low bytes of the data memory word where
the TX TDM bytes are written.
“00”=Do not write over the low byte;
“01”=Write a null byte (usually FFh);
“10”=Write silence pattern A;
“11”=Write silence pattern B.
CASWE
: CAS write enable.
“x0”=Leave CAS bits in RX Circular Buffer untouched;
“x1”=Write
RX CAS UR
in RX Circular Buffer in case of underrun;
“0x”=Write CAS bits present on the associated odd stream to the TX Circular Buffer;
“1x”=Write
TX CAS Force
field in order to bypass the CAS bits from the associated odd stream.
TX CAS Force
: TX CAS value that must be written to bypass the CAS bits from the associated odd
stream.
EI
: CAS Enable Ignore. If set, the CAS Enable bit (SFS Bit) will be ignored. Instead, the CAS will be
latched at one point for each 16/24 consecutive bytes (for E1 and T1 respectively).
RX CAS UR
: RX CAS value that will be sent in case of an underrun situation on the RX_SAR side.
CM
: Cas Monitor. When ‘1’, any change in the TX CAS value will be reported to the CPU.
Last TX CAS
: Last Value of the TX CAS received from the TDM bus.
FS Offset
: Frame Offset that must be added in order for internal and external multiframes to coincide.
Initialize to “00000” by software.
RBW
+4
+6
RX CAS UR
TX CAS Force
CASWE
FS Offset
0
Last TX CAS
CM
0
0
EI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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