參數(shù)資料
型號: MT9044AL
廠商: Mitel Networks Corporation
英文描述: T1/E1/OC3 System Synchronizer
中文描述: T1/E1/OC3系統(tǒng)同步
文件頁數(shù): 18/30頁
文件大?。?/td> 120K
代理商: MT9044AL
18
MT9044
Advance Information
Reset Circuit
A simple power up reset circuit with about a 50us
reset low time is shown in Figure 14. Resistor R
P
is
for protection only and limits current into the RST pin
during power down conditions. The reset low time is
not critical but should be greater than 300ns.
Figure 14 - Power-Up Reset Circuit
Dual T1 Reference Sources with MT9044 in
Automatic Control
For systems requiring simple state machine control,
the application circuit shown in Figure 15 using
Automatic Control may be used.
In this circuit, the MT9044 is operating Automatically,
using a Guard Time Circuit, and the LOS1 and LOS2
inputs to determine all mode changes. Since the
Guard Time Circuit is set to about 1s, all line
interruptions (LOS1=1) less than 1s will cause the
MT9044 to go from Primary Normal Mode to
Holdover Mode and not switch references. For line
interruptions greater than 1s, the MT9044 will switch
Modes from Holdover to Secondary Normal,
provided that the secondary signal is valid (LOS2=0).
After receiving a good primary signal (LOS1=0), the
MT9044 will switch back to Primary Normal Mode
For complete Automatic Control state machine
details, refer to Table 5 for the State Table, and
Figure 8 for the State Diagram.
+5V
RST
R
P
1k
C
10nF
R
10k
MT9044
Figure 15 - Dual T1 Reference Sources with MT9044 in 1.544MHz Automatic Control
1k
1k
10nF
To
TX Line
XFMR
MT8985
STo0
STi0
STo1
STi1
F0i
C4i
MT9044
F0o
C4o
FS1
FS2
GTo
GTi
PRI
SEC
LOS1
LOS2
OSCi
MS1
MS2
RSEL
To
RX Line
XFMR
To Line 1
Out
20MHz
±
32ppm
MT9074
To
TX Line
XFMR
DSTo
DSTi
F0i
C4i
TTIP
TRING
RTIP
RRING
LOS
E1.5o
To
RX Line
XFMR
To Line 2
10uF
150k
RST
TRST
10k
+
MT9074
DSTo
DSTi
F0i
C4i
TTIP
TRING
RTIP
RRING
LOS
E1.5o
CLOCK
1k
+ 5V
+ 5V
+ 5V
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