參數(shù)資料
型號: MT90221
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備(四端口ATM IMA和UNI處理器))
中文描述: 四IMA的/單向物理層設(shè)備(IMA的四端口/單向物理層設(shè)備(四端口自動柜員機IMA的和單向處理器))
文件頁數(shù): 80/116頁
文件大小: 309K
代理商: MT90221
MT90221
72
7.11
Interrupt Registers Description
Tables 94 to 102 describe the
Interrupt
registers.
Address (Hex):
Direct access
Reset Value (Hex):
232
00
Bit #
Type
Description
7:4
3:0
R
R
Reserved.
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect
on the bits in this register. The status bit is not latched and changing the mask bit in the
IRQ Master Register has a direct effect on the level of the IRQ pin.
Table 94 - IRQ Master Status Register
Address (Hex):
Direct access
Reset Value (Hex):
218
00
Bit #
Type
Description
7:4
3:0
R/W
R/W
Reserved. Write 0 for normal operation.
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A ’0’ means that the IRQ level is not affected by the corresponding bit.
Table 95 - IRQ Master Enable Register
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