- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT90221 (Mitel Networks Corporation) Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90221 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| 中文描述： | 四IMA的/單向物理層設(shè)備（IMA的四端口/單向物理層設(shè)備（四端口自動(dòng)柜員機(jī)IMA的和單向處理器）） |
| 文件頁(yè)數(shù)： | 17/116頁(yè) |
| 文件大?。?/td> | 309K |
| 代理商： | MT90221 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
MT90221
9
It also provides the content for received ICP cells
that contain some changes. The external T1 or E1
framers provide the low level status of the link. The
software integrates and responds to the various
events.
1.2
The MT90221 circuitry implements the following
functions:
UTOPIA L2 Interface
verification of the incoming HEC (optional)
generation of a new HEC byte
transmit scheduler
generation of the TX IMA Data Cell Rate (IDCR)
generation and insertion of ICP cells, Filler
Cells and Stuff Cells in IMA mode
generation of Idle Cells in UNI mode (from on-
chip copies of the cells)
flexible PCM formatting of the outgoing bytes
retrieval of ATM Cells from the incoming PCM
format
cell delineation
retrieval and processing of ICP cells
synchronization of the IMA Frame
management of the internal re-sequencer RX
links (when active)
extraction of the RX IDCR
verification of the delays between-links
re-sequencing of ATM cells using external
Static RAM
various performance monitoring counters
8-bit microprocessor interface (adaptable to
Intel or Motorola interfaces)
Hardware Functions
The MT90221 can be separated into four major
independent blocks and three support blocks.
The four major independent blocks are:
the ATM Transmit Path
the ATM Receive Path
the PCM Interface
the UTOPIA Interface
The three support blocks are:
the Counter Block
the Interrupt Block
the Microprocessor Interface Block
2.0 The ATM Transmit Path
The transmit path corresponds to a cell flow from the
ATM Layer towards the T1/E1 interface. The ATM cell
path on the transmit side starts at the UTOPIA L2
Interface. Once ATM cells are received at the
UTOPIA port, the device transfers these cells to the
transmit block.
The MT90221 provides ATM cell mapping and
transmission convergence blocks to transport ATM
cell payloads over four flexible PCM Interface ports.
It uses these PCM Interface ports to communicate
with most off-the-shelf T1 or E1 framers.
Each of the four T1/E1 links can be assigned to
either an IMA Group or to an UNI link. A single T1/E1
link cannot be assigned to more than one IMA
Group.
The functional block diagram at Figure 3 illustrates
the transmit function of the MT90221.
2.1
In general terms, the MT90221 transmit input port
has the following properties:
cell level handshaking complies with the ATM
Forum UTOPIA L2 Specification
behaves like a UTOPIA MPHY Device
each port can be enabled or disabled
independently
generates and optionally verifies the HEC for
incoming cells
includes the ATM Forum polynomial when
generating the HEC (default option that can be
disabled)
either passes or removes incoming Idle cells
either passes or removes incoming Unassigned
cells
provides a counter per UTOPIA port for the total
number of Idle and Unassigned cells (24 bits)
provides a counter per UTOPIA port for the total
number of cells with wrong incoming HEC (24
bits)
provides a counter per UTOPIA port for the total
number of cells handled (24 bits)
The input port can be enabled to remove (filter)
Unassigned or Idle cells. If Unassigned or Idle Cell
Filtering is enabled, the device checks for and
discards Unassigned or Idle cells. This function is
programmed in the
UTOPIA Input Control
register.
Cell_In_Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| MT9042B | () |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。