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參數(shù)資料
| 型號： | MT8941B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL(先進的T1/CEPT數(shù)字中繼鎖相環(huán)) |
| 中文描述： | 高級T1/CEPT數(shù)字集群鎖相環(huán)（先進的T1/CEPT數(shù)字中繼鎖相環(huán)） |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MT8941B |
MT8941B
CMOS
6
The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchro-nized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode. When
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz on to which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2. In both these
modes, this internal signal is available on C8Kb (pin
10) and DPLL #2 locks to the falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the falling edge
of the 8 kHz signal on C8Kb.
Minor modes of DPLL #2
The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).
Table 4. Summary of Modes of Operation - DPLL #1 and #2
Mode
#
M
S
0
M
S
1
M
S
2
M
S
3
Operating Modes
DPLL #1
DPLL #2
0
0
0
0
0
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the input
frame pulse (F0i).
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.
1
0
0
0
1
NORMAL MODE
NORMAL MODE:
F0b is an input but has no function in this mode.
2
0
0
1
0
NORMAL MODE
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
3
0
0
1
1
NORMAL MODE
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
4
0
1
0
0
DIVIDE-1 MODE
Same as mode ‘0’.
5
0
1
0
1
DIVIDE-1 MODE
SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.
6
0
1
1
0
DIVIDE-1 MODE
Same as mode 2.
7
0
1
1
1
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
8
1
0
0
0
NORMAL MODE
Same as mode ‘0’.
9
1
0
0
1
NORMAL MODE
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
10
1
0
1
0
NORMAL MODE
Same as mode 2.
11
1
0
1
1
NORMAL MODE
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
12
1
1
0
0
DIVIDE-2 MODE
Same as mode ‘0’.
13
1
1
0
1
DIVIDE-2 MODE
SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.
14
1
1
1
0
DIVIDE-2 MODE
Same as mode 2.
15
1
1
1
1
DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8941B | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8950 | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| MT8950AC | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
| MT8941BPR | 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8941BPR1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG.TRUNK PLL EOL160209 |
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