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參數(shù)資料
| 型號(hào)： | MT8941B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL(先進(jìn)的T1/CEPT數(shù)字中繼鎖相環(huán)) |
| 中文描述： | 高級(jí)T1/CEPT數(shù)字集群鎖相環(huán)（先進(jìn)的T1/CEPT數(shù)字中繼鎖相環(huán)） |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MT8941B |
CMOS
MT8941B
17
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Please review the section on "Jitter Performance and Lock-in Range".
Figure 17 - Master Clock Inputs
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 18 - External Inputs on C4b and F0b for the DPLL #2
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 14)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
C
L
O
C
K
S
Master clocks input rise time
t
r
t
f
10
ns
2
Master clocks input fall time
10
ns
3
Master clock period
(12.352MHz)*
t
P12
80.943
80.958
80.974
ns
For DPLL #1, while operating to
provide the T1 clock signal.
4
Master clock period
(16.384MHz)*
t
P16
61.023
61.035
61.046
ns
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
5
Duty Cycle of master clocks
45
50
55
%
6
Lock-in Range
DPLL #1
DPLL #2
-2.33
-1.69
+2.33
+1.69
Hz
With the Master frequency
tolerance at
±
32 ppm.
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 18)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
F0b input pulse width (LOW)
t
WFP
t
P4o
t
FS
t
FH
244
ns
2
C4b input clock period
244
ns
3
Frame pulse (F0b) setup time
50
ns
4
Frame pulse (F0b) hold time
25
ns
Master clock
inputs
2.4 V
1.5 V
0.4 V
t
r
t
f
t
P12
or t
P16
F0b
C4b
V
IH
V
IL
V
IH
V
IL
t
FS
t
WFP
t
FH
t
P4o
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8941B | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8950 | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| MT8950AC | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
| MT8941BPR | 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8941BPR1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG.TRUNK PLL EOL160209 |
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