參數(shù)資料
型號(hào)： MT8930B
廠商： Mitel Networks Corporation
英文描述： ()
中文描述： （）
文件頁(yè)數(shù)： 13/29頁(yè)
文件大小： 277K
代理商： MT8930B
Application Note
MSAN-141
A-213
Figure 13 - ST-BUS Channel Assignment
information to and from the S or ST-BUS. In
the TE mode, timing is generated from an on-board
analog phase-locked loop which extracts timing from
the received data on the S-Bus and generates the
system 4096 kHz (C4b) and frame pulse (F0b). The
analog phase-locked loop also maintains proper
phase relation between the timing signals as well as
filtering out jitter which may be present on the
received line signal. Please refer to section 5.3 “PLL
and Jitter” for more details.
3.2
Channel Assignment
The SNIC makes use of three types of channels to
transmit and receive data and control/status to and
from the S-interface port. These are the B, D and
C-channels.
The B1 and B2 channels each have a bandwidth of
64 kbit/s and are used to carry PCM voice or data
across the network.
The D-channel is primarily intended to carry
signalling information for circuit switching through the
ISDN network. The SNIC provides the capability of
having a 16 kbit/s or full 64 kbit/s D-channel by
allocating the B1-channel timeslot on the S-Bus to
the D-channel.
The C-channel provides a means for the system to
control and monitor the functions of the SNIC. This
control/status channel is accessed by the system
through the ST-BUS or microprocessor port. The
C-channel provides access to two registers which
provide complete control over the state activation
machine, the D-channel priority mechanism as well
as the various maintenance functions. These
channels are transferred to the SNIC using the first
four channels on the DSTi and DSTo lines of the ST-
BUS interface (refer to Figure 13). To simplify the
channel assignment of a full ST-BUS stream, the
SNIC supplies a delayed frame pulse (F0od) which
can be used in a daisy chain configuration. The first
SNIC in the chain will receive the system frame pulse
with the following devices receiving its predecessor’s
delayed output frame pulse (F0od).
3.3
System to Line Mapping
In order for system designers to get a better
understanding of the inherent delays introduced by
the S/T interface, a detailed explanation of the
throughput delays of the MT8930B/31B are required.
Figure 3 is divided into two sections with each
section having the respective line signal, transmitter
timing signals and remote receiver timing signals.
Since the S-Bus has a 4 kHz frame, the valid
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
O
O
D
F
D
D
F
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