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參數(shù)資料
| 型號： | MT58L64V36P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 64K的× 36，流水線，SCD的SyncBurst的SRAM（處理器，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 487K |
| 代理商： | MT58L64V36P |
15
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOTE:
1. V
DD
Q = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; V
DD
Q = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times
and greater output loading.
3. “ Device deselected” means device is in power-down mode as defined in the truth table. “ Device selected” means device
is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
5. This parameter is sampled.
6. Preliminary package data.
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
T
A
= 25°C; f = 1 MHz;
V
DD
= 3.3V
SY MBOL
C
I
C
O
C
A
C
CK
TY P
2.7
4
2.5
2.5
MA X
3.5
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
5
5
5
5
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C
￡
T
A
￡
+70°C; V
DD
= +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Power Supply
Current:
Operating
Power Supply
Current: Idle
CONDITIONS
SYM
TYP
-5
-6
-7.5
-10
UNITS NOTES
Device selected; All inputs
￡
V
IL
or
3
V
IH
; Cycle time
3
t
KC (MIN);
V
DD
= MAX; Outputs open
Device selected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
3
V
IH
; All inputs
￡
V
SS
+ 0.2 or
3
V
DD
- 0.2;
Cycle time
3
t
KC (MIN)
Device deselected; V
DD
= MAX;
All inputs
￡
V
SS
+ 0.2 or
3
V
DD
- 0.2;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
All inputs
￡
V
IL
or
3
V
IH
;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
3
V
IH
; All inputs
￡
V
SS
+ 0.2 or
3
V
DD
- 0.2;
Cycle time
3
t
KC (MIN)
I
DD
100
400
340
280
225
mA
2, 3, 4
I
DD
1
30
100
85
70
65
mA
2, 3, 4
CMOS Standby
I
SB
2
0.5
10
10
10
10
mA
3, 4
TTL Standby
I
SB
3
6
25
25
25
25
mA
3, 4
Clock Running
I
SB
4
30
100
85
70
65
mA
3, 4
MAX
FBGA CAPACITANCE
DESCRIPTION
Address/Control Input Capacitance
Output Capacitance (Q)
Clock Capacitance
CONDITIONS
SYMBOL
C
I
C
O
C
CK
TYP
2.5
4
2.5
MAX
3.5
5
3.5
UNITS
pF
pF
pF
NOTES
5, 6
5, 6
5, 6
T
A
= 25°C; f = 1 MHz
相關PDF資料 |
PDF描述 |
|---|---|
| MT58L128L32D1 | 128K x 32，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128L36D1 | 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128L32P1 | 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128L36P1 | 128K x 36，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128V32P1 | 128K x 32， Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64V36PT-5 | 制造商:Micron Technology Inc 功能描述: |
| MT58L64V36PT-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT58LC128K18B4LG-8.5 | 制造商:Cypress Semiconductor 功能描述:128KX18 SRAM PLASTIC TQFP 3.3V |
| MT58LC128K18C6LG-7.5 | 制造商:Cypress Semiconductor 功能描述:EOL, REPLACE WITH MT58L128L18D |
| MT58LC128K18D9LG-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
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