參數(shù)資料
型號(hào)： MT58L64L32F
廠商： Micron Technology, Inc.
英文描述： 64K x 32,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
中文描述： 64K的× 32，流量通過SyncBurst的SRAM（處理器，流通式同步脈沖靜態(tài)內(nèi)存）
文件頁數(shù)： 12/24頁
文件大小： 459K
代理商： MT58L64L32F
12
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TRUTH TABLE
OPERATION
ADDRESS CE# CE2# CE2
USED
None
H
None
L
None
L
None
L
None
L
None
X
External
L
External
L
External
L
External
L
External
L
Next
X
Next
X
Next
H
Next
H
Next
X
Next
H
Current
X
Current
X
Current
H
Current
H
Current
X
Current
H
ZZ
ADSP# ADSC# ADV# WRITE# OE#
CLK
DQ
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “ Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc
pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
相關(guān)PDF資料
PDF描述
MT58L64L36F 64K x 36,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128L18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128V18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L64L32P 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L64V32P 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
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