參數(shù)資料
型號(hào): MT58L64L18F
廠商: Micron Technology, Inc.
英文描述: 64K x 18, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM)
中文描述: 64K的× 18,3.3V的I / O的流量通過(guò)SyncBurst的SRAM(1兆,3.3V的輸入/輸出,流通式同步脈沖靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 16/17頁(yè)
文件大?。?/td> 327K
代理商: MT58L64L18F
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM
MT58L64L18F.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
16
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
ADV#
Single WRITE
D(A3)
A3
A4
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
tWH
tWS
tOEHZ
tDH
tDS
tKQ
tOELZ
(NOTE 1)
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
DONT CARE
UNDEFINED
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
t
WS
t
DS
t
CES
t
AH
t
ADSH
t
WH
t
DH
t
CEH
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
READ/WRITE TIMING PARAMETERS
-7.5
-8.5
-10
SYM
t
KC
f
KF
t
KH
t
KL
t
KQ
t
OELZ
t
OEHZ
t
AS
t
ADSS
MIN
8.8
MAX
MIN
10.0
MAX
MIN
15
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
113
100
66
1.9
1.9
1.9
1.9
4.0
4.0
7.5
8.5
10.0
0
0
0
4.2
5.0
5.0
2.0
2.0
2.0
2.0
2.5
2.5
-7.5
-8.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
相關(guān)PDF資料
PDF描述
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MT58L32L36P 32K x 36, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
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