- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384757 > MT55L128L32P1 (Micron Technology, Inc.) 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) PDF資料下載
參數(shù)資料
| 型號： | MT55L128L32P1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 3.3V的I / O的128K的× 32，流量通過ZBT SRAM的電壓（3.3V輸入/輸出，4Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 434K |
| 代理商： | MT55L128L32P1 |
3
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The data associated with the address is required
two cycles later, or on the rising edge of clock cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
Please
refer
to
www.micronsemi.com/datasheets/zbtds.html) for the
Micron’s Web
site
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q),
enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst
advance pin (ADV/LD#). Use of burst mode is optional.
It is allowable to give an address for each individual
READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
GENERAL DESCRIPTION (continued)
相關PDF資料 |
PDF描述 |
|---|---|
| MT55L128L36P1 | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V或輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128V32P1 | 2.5V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L128V36P1 | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L256L18P1 | 3.3V I/O，256K x 18,Flow-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
| MT55L256V18P1 | 2.5V I/O，256K x 18,Flow-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L128L32P1T-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 5ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128L32P1T-10 IT | 制造商:Cypress Semiconductor 功能描述: |
| MT55L128L32P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128L36F1-11A | 制造商:Micron Technology Inc 功能描述: |
| MT55L128L36F1F-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。