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參數(shù)資料
| 型號： | MT4LC4M16R6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DRAM |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 339K |
| 代理商： | MT4LC4M16R6 |
2
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4 MEG x 16
FPM DRAM
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16F5 (12 row addresses)
A0-
A11
RAS#
12
12
10
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
12
10
COLUMN-
ADDRESS
BUFFER(10)
ROW-
ADDRESS
BUFFERS (12)
4,096
1,024
COLUMN
DECODER
16
REFRESH
COUNTER
R
R
D
4,096 x 1,024 x 16
MEMORY
ARRAY
C
S
1,024 x 16
4,096 x 16
NO. 2 CLOCK
GENERATOR
WE#
OE#
DQ0-
DQ15
16
16
DATA-OUT
BUFFER
CASL#
CAS#
CASH#
DATA-IN BUFFER
16
SENSE AMPLIFIERS
I/O GATING
FAST PAGE MODE ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. Use of both
CAS# signals results in a word access via the 16 I/O pins
(DQ0-DQ15). Use of only one of the two results in a
BYTE access cycle. CASL# transitioning LOW selects an
access cycle for the lower byte (DQ0-DQ7), and CASH#
transitioning LOW selects an access cycle for the upper
byte (DQ8-DQ15). General byte and word access timing
is shown in Figures 1 and 2.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
The WE# signal must be activated to execute a
WRITE operation; otherwise a READ operation will be
performed. The OE# signal must be activated to enable
the DQ output drivers for a read access and can be
deactivated to disable output data if necessary.
FAST-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the FAST-PAGE-MODE
operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4LC4M16R6-1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC4M16R6TG5 | 制造商:Micron Technology Inc 功能描述: |
| MT4LC4M16R6TG-5 | 制造商:Micron Technology Inc 功能描述: |
| MT4LC4M16R6TG-5S | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
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