參數(shù)資料
型號： MT48LC16M8A2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 41/59頁
文件大小： 1844K
代理商： MT48LC16M8A2
41
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
SELF REFRESH MODE
*CAS latency indicated in parentheses.
-7E
-75
-8E
SYMBOL*
t
CKS
t
CMH
t
CMS
t
RAS
t
RP
t
XSR
MIN
1.5
0.8
1.5
37
15
75
MAX
MIN
1.5
0.8
1.5
44
20
75
MAX
MIN
2
1
2
50
20
80
MAX
UNITS
ns
ns
ns
ns
ns
ns
120,000
120,000
120,000
TIMING PARAMETERS
-7E
-75
-8E
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
MAX
MIN
1
2
3
3
8
10
1
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON
’
T CARE
COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE
NOP
NOP
or COMMAND
INHIBIT
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
BA0, BA1
BANK(S)
(
)
(
)
(
)
(
)
High-Z
tCKS
AH
AS
AUTO
REFRESH
tRAS min
1
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tCKH
tCKS
DQM/
DQML, DQMH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
t
t
A0-A9, A11
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
(
ALL BANKS
SINGLE BANK
A10
(
)
(
)
(
)
(
)
)
)
(
)
(
)
T0
T1
T2
≥
Tn + 1
To + 1
To + 2
(
)
(
)
(
)
(
)
NOTES:
1. No maximum time limit for Self Refresh.
t
RAS max applies to non-Self Refresh mode.
2.
t
XSR requires minimum of two clocks regardless of frequency or timing.
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