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| 型號(hào)： | MT46V8M8 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8 x 4 banks DDR SDRAM(2 M x 8 x 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM) |
| 中文描述： | 2梅格× 8 × 4銀行DDR SDRAM內(nèi)存（2米× 8 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 53/69頁 |
| 文件大?。?/td> | 2369K |
| 代理商： | MT46V8M8 |
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53
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
NOTES (continued)
38. Reduced Output Drive Curves:
a)The full variation in driver pull-down current
from minimum to maximum process,
temperature and voltage will lie within the
outer bounding lines of the V-I curve of Figure
C.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure C.
c) The full variation in driver pull-up current
from minimum to maximum process,
temperature and voltage will lie within the
outer bounding lines of the V-I curve of Figure
D.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure D.
e) The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0 to V
DD
Q/2.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages
from 0.1V to 1.0 Volt.
39. The voltage levels used are derived from the
referenced test load. In practice, the voltage
levels obtained from a properly terminated bus
will provide significantly different voltage
values.
40.
V
IH
overshoot: VIH (MAX) = V
DD
Q+1.5V for a
pulse width
≤
3ns and the pulse width can not
be greater than 1/ 3 of the cycle rate. V
IL
under-
Figure D
Pull-Up Characteristics
-120
-100
-80
-60
-40
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
V
DD
Q - V
OUT
(V)
I
O
Figure C
Pull-Dow n Characteristics
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
I
O
shoot: V
IL
(MIN) = -1.5V for a pulse width
≤
3ns
and the pulse width can not be greater than 1/ 3
of the cycle rate.
41. V
DD
and V
DDQ
must track each other.
42. Note 42 is not used.
43. Note 43 is not used
44. During initialization, V
DDQ
,
V
TT
and V
REF
must be
equal to or less than V
DD
+ 0.3V.
Alternatively,
V
TT
may be 1.35V maximum during power up,
even if V
DD
/ V
DDQ
are 0 volts,
provided a
minimum of 42 ohms of series resistance is used
between the V
TT
supply and the input pin.
45. Note 45 is not used.
46.
t
RAP
≥
t
RCD.
47. Note 47 is not used.
48. Random addressing changing 50% of data
changing at every transfer.
49. Random addressing changing 100% of data
changing at every transfer.
50. CKE must be active (high) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
t
REF later.
51. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q
is similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
52. When ever the operating frequency is altered,
not including jitter, the DLL is required to be
reset and followed by 200 clock cycles.
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