參數(shù)資料
型號(hào)： MT46V64M8TG-8
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁數(shù)： 42/68頁
文件大?。?/td> 2555K
代理商： MT46V64M8TG-8
42
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
From Command
WRITE w/AP
To Command
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
Minimum delay (with concurrent auto precharge)
[1 + (BL/2)]
t
CK +
t
WTR
(BL/2) tCK
1
t
CK
1
t
CK
(BL/2) *
t
CK
[CL
RU
+ (BL/2)]
t
CK
1
t
CK
1
t
CK
READ w/AP
NOTE (continued):
3.Current state definitions:
Idle: The bank has been precharged, and
t
RP has been met.
Row Active: A row in the bank has been activated, and
t
RCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read with Auto
Precharge Enabled: See following text
–
3a
Write with Auto
Precharge Enabled: See following text
–
3a
3a.
The read with auto precharge enabled or WRITE with auto precharge enabled states can
each be broken into two parts: the access period and the precharge period. For read with
auto precharge, the precharge period is defined as if the same burst was executed with
auto precharge disabled and then followed with the earliest possible PRECHARGE com-
mand that still accesses all of the data in the burst. For write with auto precharge, the
precharge period begins when tWR ends,with tWR measured as if auto precharge was
disabled. The access period starts with registration of the command and ends where the
precharge period (or tRP) begins.
This device supports concurrent auto precharge such that when a read with auto precharge is
enabled or a write with auto precharge is enabled any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in process. In
either case, all other related limitations apply (e.g., contention between read data and write
data must be avoided).
3b.
The minimum delay from a READ or WRITE command with auto precharge enabled, to a
command to a different bank is summarized below.
CL
= CAS Latency (CL) rounded up to the next integer
BL = Bust Length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the
current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-
NATE must be used to end the READ burst prior to asserting a WRITE command.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V64M8TG-8L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
MT46V8M16 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
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