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參數(shù)資料
| 型號： | MT46V64M8TG-8 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內存 |
| 文件頁數(shù)： | 26/68頁 |
| 文件大?。?/td> | 2555K |
| 代理商： | MT46V64M8TG-8 |
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26
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 14.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in ele-
ment will be registered on the first rising edge of DQS
following the WRITE command, and subsequent data
elements will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write preamble;
the LOW state on DQS following the last data-in ele-
ment is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (
t
DQSS) is speci-
fied with a relatively wide range (from 75 percent to 125
percent of one clock cycle). All of the WRITE diagrams
show the nominal case, and where the two extreme
cases (i.e.,
t
DQSS [MIN] and
t
DQSS
[MAX]) might not
be intuitive, they have also been included. Figure 15
shows the nominal case and the extremes of
t
DQSS for
a burst of 4. Upon completion of a burst, assuming no
other commands have been initiated, the DQs will re-
main High-Z and any additional input data will be ig-
nored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE command.
In either case, a continuous flow of input data can be
maintained. The new WRITE command can be issued
on any positive edge of clock following the previous
WRITE command. The first data element from the new
burst is applied after either the last element of a com-
pleted burst or the last desired data element of a longer
burst which is being truncated. The new WRITE com-
mand should be issued
x
cycles after the first WRITE
command, where
x
equals the number of desired data
element pairs (pairs are required by the 2
n
-prefetch
architecture).
Figure 16 shows concatenated bursts of 4. An ex-
ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.
Data for any WRITE burst may be followed by a
subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst,
t
WTR should be met
as shown in Figure 19.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
Figure 14
WRITE Command
prior to the
t
WTR period are written to the internal ar-
ray, and any subsequent data-in should be masked
with DM as shown in Figure 21.
Data for any WRITE burst may be followed by a
subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst,
t
WR should
be met as shown in Figure 22.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the
t
WR period are written to the
internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until
t
RP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON
’
T CARE
x4: A0
–
A9, A11, A12
x8: A0-A9, A11
x16: A0
–
A9
x8: A12
x16:A11, A12
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相關代理商/技術參數(shù) |
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