參數(shù)資料
型號(hào)： MT46V64M8TG-75
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 63/68頁(yè)
文件大?。?/td> 2555K
代理商： MT46V64M8TG-75
63
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
BANK READ
–
WITHOUT AUTO PRECHARGE
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
t
IH
RA
t
RCD
t
RAS7
t
RC
t
RP
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ
1
DQS
Case 1:
t
AC
(
MIN)
and
t
DQSCK
(
MIN)
Case 2:
t
AC
(
MAX)
and
t
DQSCK
(
MAX)
DQ
1
DQS
t
RPRE
t
RPRE
t
RPST
t
RPST
t
DQSCK
(
MIN)
t
DQSCK
(
MAX)
t
LZ
(
MIN)
t
LZ
(
MAX)
t
AC
(
MIN)
t
LZ
(
MIN)
DO
n
t
HZ
(
MAX)
t
AC
(
MAX)
t
LZ
(
MAX)
DO
n
NOP6
NOP6
COMMAND
5
3
ACT
RA
RA
Col
n
READ2
PRE
7
Bank
x
RA
RA
RA
Bank
x
Bank
x
4
ACT
Bank
x
NOP6
NOP6
NOP6
t
HZ
(
MIN)
NOTE:
1. DO
n
= data-out from column
n
; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4.
“
Don
’
t Care
”
if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if
t
RAS minimum is met.
8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
ONE BANK
ALL BANKS
DON
’
T CARE
TRANSITIONING DATA
x4: A0-A9, A11, A12
x8: A0-A11
x16: A0-A9
x8: A12
x16: A11, A12
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MT46V64M8TG-75L DOUBLE DATA RATE DDR SDRAM
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