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參數(shù)資料
| 型號： | MSM82C54-2RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MSM82C54-2RS |
15/23
Semiconductor
MSM82C54-2RS/GS/JS
Count value writing during counting:
The count value writing does not affect the current counting sequence. If the gate trigger is
generated after the new count value is written and before the current counting ends, the new
count value is loaded to the CE at the falling edge of the next clock pulse, and counting
continues using the new count value. The various roles of the gate input signals in the above
modes are summarized in the following table.
0
1
"H" Level
"L" Level Falling Edge
Rising Edge
Mode
Gate
Counting not possible
Counting possible
(1)
(2)
Start of counting
Retriggering
2
(1)
(2)
Counting not possible
Counter output forced to "H" level
Start of counting
Counting possible
3
(1)
(2)
Counting not possible
Counter output forced to "H" level
Start of counting
Counting possible
4
Counting not possible
Counting possible
5
(1)
(2)
Start of counting
Retriggering
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