參數(shù)資料
型號(hào): MSM82C54-2RS
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24
封裝: 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-24
文件頁數(shù): 7/24頁
文件大小: 182K
代理商: MSM82C54-2RS
14/23
Semiconductor
MSM82C54-2RS/GS/JS
Odd number counting operation:
The output is initially set to “H” level. At the falling edge of the next clock pulse, the initial
count value minus one is loaded in the CE, and then the value is decremented by 2 by
consecutive clock pulses. When the counter value becomes 0, the output is set to “L” level,
and then the initial count value minus 1 is reloaded to the CE. The value is then decremented
by 2 by consecutive clock pulses. When the counter value becomes 2, the output is again set
to “H” level and the initial count value minus 1 is again reloaded. The above operations are
repeated. In other words, the output is set to “H” level during (N+1)/2 counting and to “L”
level during (N-1)/2 counting in the case of odd number counting.
Mode 4
Application: Software trigger strobe
Output operation: The output is initially set to “H” level. When the counter value becomes
0, the output goes to “L” level during one clock pulse, and then restores “H” level again.
The count sequence starts when the initial count value is written.
Gate function: “H” level validates counting, and “L” level invalidates counting. The gate
signal does not affect the output.
Count value load timing:
After the control word and initial count value are written, the count value is loaded to the CE
at the falling edge of the next clock pulse. The clock pulse does not decrement the initial count
value. If the initial count value is N, the strobe is not output unless N+1 clock pulses are input
after the initial count value is written,
Count value writing during counting:
The new count value is written to the CE at the falling edge of the next clock pulse, and
counting continues using the new count value. The operation for 2-byte count is as follows:
1) First byte writing does not affect the counting operation.
2) After the second byte is written, the new count value is loaded to the CE at the falling edge
of the next clock pulse.
This means that the counting operation is retriggered by software. The output strobe is set to
“L” level upon input of N+1 clock pulses after the new count value N is written.
Mode 5
Application: Hardware trigger strobe
Output operation:
The output is initially set to “H” level. When the counter value becomes 0 after triggering by
the rising edge of the gate pulse, the output goes to “L” level during one clock pulse, and then
restores “H” level.
Count value load timing:
Even after the control word and initial count value are written, loading to the CE does not
occur until the input of the clock pulse succeeding the trigger. For the clock pulse for CE
loading, the count value is not decremented. If the initial count value is N, therefore, the
output is not set to “L” level until N+1 clock pulses are input after triggering.
Gate function:
The initial count value is loaded to the CE at the falling edge of the clock pulse succeeding gate
triggering. The count sequence can be retriggered.
The gate pulse does not affect the output.
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