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參數資料
| 型號： | MSM82C54-2RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數據恢復及定時提取 |
| 英文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-24 |
| 文件頁數： | 13/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MSM82C54-2RS |
19/23
Semiconductor
MSM82C54-2RS/GS/JS
Null count indicates the count value finally written in the counter register (CR) has been
loaded in the counter element (CE). The time when the count value was loaded in the CE
depends on the mode of each counter, and it cannot be known by reading the counter value
because the count value does not tell the new count value if the counter is latched. The null
count operation is shown below.
Operation
Result
A. Control word register writing
Null count = 1
B. Count register (CR) writing
Null count = 1
C. New count loading to CE (CRCE)
Null count = 0
Note: The null count operation for each counter is independent. When the 2-byte count
is programmed, the null count is set to 1 when the count value of the second byte
is written.
If status latching is carried out multiple times before status reading, other than the first
status latch is ignored.
Simultaneous latching of the count and status of the selected counter is also possible. For
this purpose, set bits D4 and D3, COUNT and STATUS bits, to 00. This is functionally the
same as writing two separate read back commands at the same time. If counter/status
latching is carried out multiple times before each reading, other than the first one is ignored
here again. The example is shown below.
Note:
The latch command at this time point is ignored, and the first latch command is valid.
If both the count and status are latched, the status latched in the first counter read operation
is read. The order of count latching and status latching is irrelevant.
The count(s) of the next one or two reading operations is or are read.
Note:
There is the possibility of glitch noise in the output low level when reading out the data.
Peak voltage in typical condition (5 V, 25
°C) is approximately 1V and in the worst
condition (5.5 V, –40
°C) is approximately 1.4V.
Counter 0
Counter 1
Command
Counter 2
Contents
D7 D6 D5 D4 D3 D2 D1 D0
1
0000
10
1
1001
00
1
1011
00
1
0110
00
1
0001
00
1
1000
10
Count Status Count Status Count Status
Read back status and count
(counter 0)
Read back status (counter 1)
Read back status (counter 1 and 2)
Read back status (counter 2)
Read back status and count
(counter 1)
Read back status (counter 0)
L
(NOTE)
L—
—
LL
—
L
—
LL
—
L
—L
LL
—
L
LL
L
LL
L
LL
L
1
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