- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98044 > MSM6262-XXGS-BK (OKI ELECTRIC INDUSTRY CO LTD) 48 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | MSM6262-XXGS-BK |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 48 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 383K |
| 代理商： | MSM6262-XXGS-BK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Semiconductor
MSM6262-xx
29/52
9. LCD Display Circuit (COM1 to COM48, DO, CP, LOAD, DF)
The MSM6262-xx is provided with COMMON signal output. So, maximum 160 characters
can be displayed when it is used together with SEGMENT drivers (MSM5259 or MSM5839C).
Interface between MSM6262-xx and SEGMENT drivers can be done by using DO, CP, LOAD
and DF.
The SEGMENT data is serially output from DO pin, synchronized with the pulse which is
output from the CP pin.
This data, input to the SEGMENT driver, is converted from serial data to parallel data by the
latch pulse which is output from the LOAD pin of MSM6262-xx and this converted data is
used as the display data. This parallel/serial conversion is performed synchronized with the
COMMON signal of MSM6262-xx and LCD display AC signal which is output from DF pin.
So, this signal can drive dot matrix LCD panel.
10. Reset Circuit
Power-on-reset is required for MSM6262-xx when it is powered-on. So, a capacitor has to be
connected between RESET pin and VSS pin.
It is also advisable to connect a diode between RESET pin and VDD pin when it is required to
connect a capacitor of more than 3.3
F to RESET pin.
When the power-on reset circuit normally operates, the busy flags 1 and 2 become at "H" level
for about 10 ms after the power-on. During this period, a initialization of MSM6262-xx is
performed by following procedures.
1 Display is cleared
2 CG ROM becomes enabled
3 No display shift
4 ADC is incremented
5 2-line display mode
6 5 x 8 dots font configuration
7 No display shift for "g", "j", "p", "q" and "y"
8 Display off
9 No display of cursor, blinking and underline
11. Data Bus with CPU
MSM6262-xx can be interfaced with 8-bit CPU, such as 6809, Z80, 80C49 and 80C51. When
MSM6262-xx is connected with 6809, the 68 series/80 series pin has to be connected to VDD.
When MSM6262-xx is connected with Z80, 80C49 or 80C51, the 68 series/80 series pin has to
be connected to VSS. The level at 68 series/80 series cannot be switched during MSM6262-xx's
operation. It must be connected with either VDD or VSS before MSM6262-xx is turned on.
Note: It is possible, indeed, to change the 68 series/ 80 series pin's level when a reset signal
is being input to RESET pin. However, the 68 series /80 series pin does not have
characteristics to have an interface with MCU, nor does it have an antichattering
circuit.
Further, if a reset signal is input, the MSM6262-xx is initialized as described above.
So, in this case, changing the 68 series/80 series pin level is not recommended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM63182A-XXX | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC107 |
| MSM63184-XXX | 4-BIT, MROM, MICROCONTROLLER, UUC |
| MSM63184-XXXGS-K | 4-BIT, MROM, MICROCONTROLLER, PQFP128 |
| MSM63184B-XXX | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC123 |
| MSM63188-XXX | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC159 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM6295 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4-CHANNEL MIXING ADPCM VOICE SYNTEHSIS LSI |
| MSM6295GS-2K | 制造商:ROHM Semiconductor 功能描述: |
| MSM6295GS-K | 制造商:OKI Semiconductor 功能描述:Speech Recording IC |
| MSM62X42 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:REAL TIME CLOCK IC WITH BUILT-IN CRYSTAL |
| MSM62X42B | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:REAL TIME CLOCK IC WITH BUILT-IN CRYSTAL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。