參數(shù)資料
型號： MSC8154ETVT1000B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 24/68頁
文件大?。?/td> 912K
代理商： MSC8154ETVT1000B
MSC8154E Quad-Core Digital Signal Processor with Security Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor
30
2.5.2.2
SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK.
Figure 5 shows a receiver reference diagram of the SerDes reference clocks.
The characteristics of the clock signals are as follows:
The supply voltage requirements for VDDSXC are as specified in Table 3.
The SerDes reference clock receiver reference circuit structure is as follows:
—The SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in
Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-
Ω
termination to GNDSXC followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V
/ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SR[1–2]_REF_CLK and SR[1–2]_REF_CLK inputs cannot drive 50
Ω to GND
SXC DC or
the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled
externally.
The input amplitude requirement is described in detail in the following sections.
Figure 5. Receiver of SerDes Reference Clocks
Input
Amp
50
Ω
50
Ω
SR[1–2]_REF_CLK
相關PDF資料
PDF描述
MSC8252TVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8252SVT1000B 0-BIT, OTHER DSP, PBGA783
MSD1010LT3 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR
MSD1010LT1 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR
MMBT1010LT3 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-236AB
相關代理商/技術參數(shù)
參數(shù)描述
MSC8154EVT1000B 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk
MSC8154SVT1000A 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 4-CORES - Bulk
MSC8154SVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP StarCore 6-cores RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MSC8154TVT1000A 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 4-CORES - Bulk
MSC8154TVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP StarCore 6-cores RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*