參數(shù)資料
型號: MSC8144E
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core Digital Signal Processor
中文描述: 四核心數(shù)字信號處理器
文件頁數(shù): 72/80頁
文件大?。?/td> 1145K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Hardware Design Considerations
Freescale Semiconductor
72
3.4.4.3
GE1 and GE2 Management Pins
GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that
is,
V
DDGE2
is connected to GND),
Table 66
lists the recommended management pin connections.
3.4.5
UTOPIA/POS Related Pins
Table 67
lists the board connections of the UTOPIA/POS pins when the entire UTOPIA/POS interface is not used or subset of
UTOPIA/POS interface is used. For multiplexing options that select a subset of the UTOPIA/POS interface, use the connections
described in
Table 67
for those signals that are not selected.
Table 67
assumes that the alternate function of the specified pin is
not used. If the alternate function is used, connect that pin as required to support the selected function.
GE2_SGMII_RX
GND
SXC
GE2_SGMII_TX
NC
GE2_SGMII_TX
NC
GE2_TCK
NC
GE2_TD[0–3]
NC
GE2_TX_EN
NC
Table 66. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used
Signal Name
Pin Connection
GE_MDC
NC
GE_MDIO
NC
Table 67. Connectivity of UTOPIA/POS Related Pins When UTOPIA/POS Interface Is Not Used
Signal Name
Pin Connection
UTP_IR
GND
UTP_RADDR[0–4]
V
DDIO
UTP_RCLAV_PDRPA
NC
UTP_RCLK
GND
UTP_RD[0–15]
GND
UTP_REN
V
DDIO
UTP_RPRTY
GND
UTP_RSOC
GND
UTP_TADDR[0–4]
V
DDIO
UTP_TCLAV
NC
UTP_TCLK
GND
UTP_TD[0–15]
NC
UTP_TEN
V
DDIO
UTP_TPRTY
NC
UTP_TSOC
NC
V
DDIO
3.3 V
Table 65. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)
Signal Name
Pin Connection
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