參數(shù)資料
型號: MSC8144E
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core Digital Signal Processor
中文描述: 四核心數(shù)字信號處理器
文件頁數(shù): 29/80頁
文件大?。?/td> 1145K
代理商: MSC8144E
Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
29
all four cores. It was created using CodeWarrior
3.0. These values are provided as examples only. Power consumption is
application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining
proper operating temperatures, evaluate power consumption for your application and use the design guidelines in
Section 3
of
this document.
At allowable voltage levels,
Table 7
lists the estimated power dissipation on the 1.0-V AV
DD
supplies for the MSC8144E PLLs.
Table 7. MSC8144E PLLs Power Dissipation
2.6
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8144E.
2.6.1
DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E.
Note:
DDR SDRAM uses V
DDDDR
(typ) = 2.5 V and DDR2 SDRAM uses V
DDDDR
(typ) = 1.8 V.
2.6.1.1
DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 8
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when
V
DDDDR
(typ) = 1.8 V.
PLL supply
Typical
Maximum
Unit
V
DDPLL0
TBD
10
mW
V
DDPLL1
TBD
10
mW
V
DDPLL2
TBD
10
mW
Note:
Typical value is based on V
DDPLLX
= 1.0 V, T
A
= 70°C, T
J
= 105°C.
Table 8. DDR2 SDRAM DC Electrical Characteristics for V
DDDDR
(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
I/O supply voltage
1
V
DDDDR
1.7
1.9
V
I/O reference voltage
2
MV
REF
0.49
×
V
DDDDR
0.51
×
V
DDDDR
V
I/O termination voltage
3
V
TT
MV
REF
– 0.04
MV
REF
+ 0.04
V
Input high voltage
V
IH
MV
REF
+ 0.125
V
DDDDR
+ 0.3
M
V
REF
– 0.125
V
Input low voltage
V
IL
–0.3
V
Output leakage current
4
I
OZ
–50
50
μ
A
Output high current (V
OUT
= 1.420 V)
I
OH
–13.4
mA
Output low current (V
OUT
= 0.280 V)
I
OL
13.4
mA
Notes:
1.
2.
V
DDDDR
is expected to be within 50 mV of the DRAM V
DD
at all times.
MV
REF
is expected to be equal to 0.5
×
V
DDDDR
, and to track V
DDDDR
DC variations as measured at the receiver.
Peak-to-peak noise on MV
REF
may not exceed
±
2% of the DC value.
V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV
REF
. This rail should track variations in the DC level of V
DDDDR
.
Output leakage is measured with all outputs are disabled, 0 V
V
OUT
V
DDDDR
.
3.
4.
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