參數(shù)資料
型號(hào): MSC8144E
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: Quad Core Digital Signal Processor
中文描述: 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 38/80頁(yè)
文件大小: 1145K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
38
2.7.3.3 Reset Timing Tables
Table 24
and
Figure 8
describe the reset timing for a reset configuration.
See also Reset Errata for PLL lock and reset duration.
2.7.4
DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.7.4.1
DDR SDRAM Input Timings
Table 25
provides the input AC timing specifications for the DDR SDRAM when
V
DDDDR
(typ) = 2.5 V.
Table 24. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Max
Min
Unit
1
Required external PORESET duration minimum
25 MHz <= CLKIN < 44 MHz
44 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN < 100 MHz
100 MHz <= CLKIN < 133 MHz
32/CLKIN
1280
728
485
320
727
484
320
241
ns
ns
ns
ns
2
Delay from de-assertion of external PORESET to HRESET deassertion for
external pins and hard coded RCW
25 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN <= 133 MHz
Delay from de-assertion of external PORESET to HRESET deassertion for
loading RCW the I
2
C interface
25 MHz <= CLKIN < 44 MHz
44 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN < 100 MHz
100 MHz <= CLKIN < 133 MHz
15369/CLKIN
34825/CLKIN
92545/CLKIN
107435/CLKIN
124208/CLKIN
157880/CLKIN
615
528
3702
2441
1882
1579
233
262
2103
1627
1242
1187
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
3
Delay from HRESET deassertion to SRESET deassertion
REFCLK = 25 MHz to 133 MHz
16/CLKIN
640
120
ns
Note:
Timings are not tested, but are guaranteed by design.
Figure 8. Timing for a Reset Configuration Write
Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
V
IL
MV
REF
– 0.31
V
PORESET
Input
HRESET
Output (I/O)
SRESET
Output (I/O)
RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG
pins must be valid
1
2
3
Reset configuration write
sequence during this
period.
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