參數(shù)資料
型號： MSC8122VT8000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號處理器
文件頁數(shù)： 40/88頁
文件大?。?/td> 983K
代理商： MSC8122VT8000
MSC8122 Technical Data, Rev. 13
2-6
Freescale Semiconductor
Specifications
2.5.3
The following sections include a description of clock signal characteristics.
Table 2-6
shows the maximum
frequency values for internal (Core, Reference, Bus, and DSI) and external (
CLKIN
and
CLKOUT
) clocks. The user
must ensure that maximum frequency values are not exceeded.
Clock and Timing Signals
Figure 2-3.
Start-Up Sequence with V
DD
Raised Before V
DDH
with CLKIN Started with V
DDH
Table 2-6.
Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
Core frequency = 300 MHz
Core frequency = 400/500 MHz
External clock frequency (CLKIN or CLKOUT)
300/400/500
100/133/166
100/133/166
HCLKIN
≤
(min{70 MHz, CLKOUT})
HCLKIN
≤
(min{100 MHz, CLKOUT})
100/133/166
Table 2-7.
Clock Frequencies
Characteristics
Symbol
300 MHz Device
400 MHz Device
500 MHz Device
Min
Max
Min
Max
Min
Max
CLKIN frequency
F
CLKIN
F
BCLK
F
REFCLK
F
CLKOUT
F
CORE
20
100
20
133.3
20
166.7
BCLK frequency
40
100
40
133.3
40
166.7
Reference clock (REFCLK) frequency
40
100
40
133.3
40
166.7
Output clock (CLKOUT) frequency
40
100
40
133.3
40
166.7
SC140 core clock frequency
200
300
200
400
200
500
Note:
The rise and fall time of external clocks should be 3 ns maximum
Table 2-8.
System Clock Parameters
Characteristic
Min
Max
Unit
Phase jitter between BCLK and CLKIN
CLKIN frequency
CLKIN slope
PLL input clock (after predivider)
—
20
—
20
0.3
ns
MHz
ns
MHz
see
Table 2-7
3
100
V
Time
o.5 V
3.3 V
1.2 V
V
DDH
Nominal
PORESET/TRST asserted
V
DD
Nominal
CLKIN starts toggling
V
DD
applied
PORESET/TRST deasserted
1
V
DDH
applied
V
DDH
= Nominal
V
DD
= Nominal
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