參數(shù)資料
型號： MSC8122VT8000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號處理器
文件頁數(shù)： 4/88頁
文件大小： 983K
代理商： MSC8122VT8000
MSC8122 Technical Data, Rev. 13
iv
Freescale Semiconductor
Features
Features
Feature
Description
SC140 Cores
Four SC140 cores:
Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.
A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2 memory).
Each SC140 core provides the following:
Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate
command with the associated data move and pointer update.
4 ALUs per SC140 core.
16 data registers, 40 bits each.
27 address registers, 32 bits each.
Hardware support for fractional and integer data types.
Very rich 16-bit wide orthogonal instruction set.
Up to six instructions executed in a single clock cycle.
Variable-length execution set (VLES) that can be optimized for code density and performance.
IEEE
Std 1149.1 JTAG port.
Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.
Each SC140 core is embedded within an extended core that provides the following:
224 KB M1 memory that is accessed by the SC140 core with zero wait states.
Support for atomic accesses to the M1 memory.
16 KB instruction cache, 16 ways.
A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.
External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.
Programmable interrupt controller (PIC).
Local interrupt controller (LIC).
476 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and
accessible from all four SC140 cores using the MQBus.
4 KB bootstrap ROM.
A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.
Data bus access of up to 128-bit read and up to 64-bit write.
Operation at the SC140 core frequency.
A central efficient round-robin arbiter controlling SC140 core access on the MQBus.
Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.
Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system
buses and other modules.
PLL values are determined at reset based on configuration signal values.
64/32-bit data and 32-bit address 60x bus.
Support for multiple-master designs.
Four-beat burst transfers (eight-beat in 32-bit wide mode).
Port size of 64, 32, 16, and 8 controlled by the internal memory controller.
Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to
access internal resources.
Slave support, direct access by an external host to internal resources including the M1 and M2 memories.
On-device arbitration between up to four master devices.
A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host
processor.
21–25 bit address, 32/64-bit data.
Direct access by an external host to internal and external resources, including the M1 and the M2 memories as
well as external devices on the system bus.
Synchronous and asynchronous accesses, with burst capability in the synchronous mode.
Dual or Single strobe modes.
Write and read buffers improve host bandwidth.
Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.
Sliding window mode enables access with reduced number of address pins.
Chip ID decoding enables using one
CS
signal for multiple DSPs.
Broadcast
CS
signal enables parallel write to multiple DSPs.
Big-endian, little-endian, and munged little-endian support.
64-bit DSI, 32-bit system bus.
32-bit DSI, 64-bit system bus.
32-bit DSI, 32-bit system bus.
Extended Core
Multi-Core Shared
Memories
M2-Accessible Multi-
Core Bus (MQBus)
Internal PLL
60x-Compatible
System Bus
Direct Slave
Interface (DSI)
3-Mode Signal
Multiplexing
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