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參數(shù)資料
| 型號： | MSC8122VT8000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 22/88頁 |
| 文件大小： | 983K |
| 代理商： | MSC8122VT8000 |
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MSC8122 Technical Data, Rev. 13
1-12
Freescale Semiconductor
Signals/Connections
IRQ1
DP1
DACK1
EXT_BG2
Input
Input/ Output
Output
Output
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity
1
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and
D[8–15].
DMA Acknowledge 1
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
External Bus Grant 2
2
The MSC8122 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
DACK2
EXT_DBG2
Input
Input/ Output
Output
Output
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and
D[16–23].
DMA Acknowledge 2
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
External Data Bus Grant 2
2
The MSC8122 asserts this pin to grant data bus ownership to an external bus master.
IRQ3
DP3
DREQ2
EXT_BR3
Input
Input/ Output
Input
Input
Interrupt Request 3
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 3
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and
D[24–31].
DMA Request 2
Used by an external peripheral to request DMA service.
External Bus Request 3
2
An external master should assert this pin to request bus ownership from the internal arbiter.
IRQ4
DP4
DACK3
EXT_DBG3
Input
Input/ Output
Output
Output
Interrupt Request 4
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 4
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and
D[32–39].
DMA Acknowledge 3
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
External Data Bus Grant 3
2
The MSC8122 asserts this pin to grant data bus ownership to an external bus master.
Table 1-5.
DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC81250M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS |
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| MSC8126_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor |
| MSC8126_V15 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor |
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