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參數(shù)資料
| 型號： | MSC7116VM1000 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| 中文描述： | 低成本16位數(shù)字信號處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC |
| 文件頁數(shù)： | 47/56頁 |
| 文件大?。?/td> | 719K |
| 代理商： | MSC7116VM1000 |
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Hardware Design Considerations
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Freescale Semiconductor
47
3.4.3
Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the
CLKIN
pin. Thus, the device operates
slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher
speed. The MSC7116 can boot from an external host through the HDI16 or download a user program through the I
2
C port. The
boot operating mode is set by configuring the
BM[0–3]
signals sampled at the rising edge of
PORESET,
as shown in
Table 35
.
See the
MSC711x Reference Manual
for details of boot program operation.
3.4.3.1
HDI16 Boot
If the MSC7116 device boots from an external host through the HDI16, the port is configured as follows:
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
Table 35. Boot Mode Source Selection
BM[3–0]
Boot
Port
Input Clock
Frequency
Clock
Divide
PLL
CKSEL
RNG
Bit
Core Clock
Frequency
Comments
HDI Boot Modes
0000
HDI16
<
F
max
N/A
N/A
00
0
<
F
max
Not clocked by the PLL.
Can boot as 8- or 16-bit HDI.
Can boot as 8- or 16-bit HDI.
0101
0010
0111
0100
HDI16
HDI16
HDI16
HDI16
22.2-25 MHz
25-33.3 MHz
33-66 MHz
44.3-50 MHz
1
2
3
2
12
32
12
12
11
01
11
11
1
1
1
1
266–300 MHz
200–266 MHz
132–264 MHz
266–300 MHz
SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins
1000
SPI (SW)
1001
SPI (SW)
1010
SPI (SW)
1011
SPI (SW)
SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins
1100
SPI (SW)
<
F
max
15.6-25 MHz
33-50 MHz
44.3-75 MHz
N/A
1
2
3
N/A
17
16
18
00
11
11
11
0
0
0
0
<
F
max
The boot program automatically
determines whether EEPROM
or Flash memory.
133–212.5 MHz
132–200 MHz
133–225 MHz
<
F
max
N/A
N/A
00
0
<
F
max
Boots through different set of
pins.
I
2
C Boot Modes
0001
I
2
C
< 100 MHz
N/A
N/A
00
0
<
100 MHz
Not clocked by the PLL.
I
2
C is limited to a maximum bit
rate of 400 Kbps. With a clock
divider of 128, this limits the
maximum input clock frequency
to 100 MHz.
Reserved
0011
0110
1101
1110
1111
Notes:
Reserved
Reserved
Reserved
Reserved
Reserved
The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.
The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.
F
max
is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.
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