參數(shù)資料
型號(hào)： MSC7116VM1000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述： 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁數(shù)： 44/56頁
文件大?。?/td> 719K
代理商： MSC7116VM1000
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Hardware Design Considerations
Freescale Semiconductor
44
Power consumption.
You can reduce power consumption in your design by controlling the power consumption of the
following regions of the device:
—
Extended core.
Use the SC1400 Stop and Wait modes by issuing a
stop
or
wait
instruction.
—
Clock synthesis module.
Disable the PLL, timer, watchdog, or DDR clocks or disable the
CLKO
pin.
—
AHB subsystem.
Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
—
Peripheral subsystem.
Halt the individual on-device peripherals such as the DDR memory controller, Ethernet
MAC, HDI16, TDM, UART, I
2
C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the
MSC711x Reference Manual
.
Power supply design
. One of the most common ways to derive power is to use either a simple fixed or adjustable linear
regulator. For the system I/O voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable
linear regulator supply for the core voltage V
DDC
should be implemented. For the memory power supply, regulators
are available that take care of all DDR power requirements.
3.3
Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculated for individual design conditions. Overall power is
derived by totaling the power used by each of the major subsystems:
P
TOTAL
= P
CORE
+ P
PERIPHERALS
+ P
DDRIO
+ P
IO
+ P
LEAKAGE
Eqn. 3
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C
×
V
2
×
F
×
10
–3
mW
Eqn. 4
where,
C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
3.3.1
Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load
capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 266 MHz. This yields:
P
CORE
= 750 pF
×
(1.2 V)
2
×
266 MHz
×
10
–3
= 287 mW
Eqn. 5
This equation allows for adjustments to voltage and frequency if necessary.
Table 33. Recommended Power Supply Ratings
Supply
Symbol
Nominal Voltage
Current Rating
Core
V
DDC
1.2 V
1.5 A per device
Memory
V
DDM
2.5 V
0.5 A per device
Reference
V
REF
1.25 V
10 μA per device
I/O
V
DDIO
3.3 V
1.0 A per device
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