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參數(shù)資料
| 型號(hào)： | MSC7116VM1000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| 中文描述： | 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC |
| 文件頁數(shù)： | 43/56頁 |
| 文件大?。?/td> | 719K |
| 代理商： | MSC7116VM1000 |
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Hardware Design Considerations
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Freescale Semiconductor
43
Power planes
. Each power supply pin (
V
DDC
,
V
DDM,
and
V
DDIO
) should have a low-impedance path to the board power
supply. Each
GND
pin should be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on the device. The MSC7116
V
DDC
power supply pins should be bypassed to ground using decoupling
capacitors. The capacitor leads and associated printed circuit traces connecting to device power pins and
GND
should
be kept to less than half an inch per capacitor lead. A minimum four-layer board that employs two inner layers as power
and
GND
planes is recommended. See
Section 3.5
for DDR Controller power guidelines.
Decoupling.
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use
standard capacitor values of 0.01
μ
F for every two to three voltage pins. For core voltage decoupling, use two levels
of decoupling. The first level should consist of a 0.01 μF high frequency capacitor with low effective series resistance
(ESR) and effective series inductance (ESL) for every two to three voltage pins. The second decoupling level should
consist of two bulk/tantalum decoupling capacitors, one 10
μ
F and one 47
μ
F, (with low ESR and ESL) mounted as
closely as possible to the MSC7116 voltage pins. Additionally, the maximum drop between the power supply and the
DSP device should be 15 mV at 1 A.
PLL power supply filtering
. The MSC7116
V
DDPLL
power signal provides power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to this pin should be filtered with capacitors that have low and
high frequency filtering characteristics.
V
DDPLL
can be connected to V
DDC
through a 20
Ω
resistor. V
SSPLL
can be tied
directly to the
GND
plane. A circuit similar to the one shown in
Figure 31
is recommended. The PLL loop filter should
be placed as closely as possible to the
V
DDPLL
pin (which are located on the outside edge of the silicon package) to
minimize noise coupled from nearby circuits.The 0.01 μF capacitor should be closest to
V
DDPLL
, followed by the 0.1
μF capacitor, the 10 μF capacitor, and finally the 20-
Ω
resistor to
V
DDC
. These traces should be kept short.
Figure 30. Voltage Sequencing
Figure 31. PLL Power Supply Filter Circuits
Time
V
Differential should always be
0.7 V or more.
0.7 V or More
0.7 V or More
Ramp-down
Ramp-up
V
DDIO
= 3.3 V
V
DDM
= 2.5 V
V
DDC
= 1.2 V
V
DDC
V
DDPLL
20
Ω
0.1 μF 0.01 μF
10 μF
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| MSC7118 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller |
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