參數(shù)資料
型號(hào): MSC1210Y2PAGT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 77/94頁(yè)
文件大?。?/td> 913K
代理商: MSC1210Y2PAGT
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
79
Accumulator (A or ACC)
7
6
5
4
3
2
1
0
Reset Value
SFR E0h
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00h
ACC.70
Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 70
Summation/Shifter Control (SSCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E1h
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit
SUMR30 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.
SSCON10 Summation/Shift Count.
bits 76
SOURCE
SSCON1
SSCON0
MODE
CPU
0
Values written to the SUM registers are accumulated when the SUMR0 value is written (sum/shift ignored)
ADC
0
1
Summation register Enabled. Source is ADC, summation count is working.
CPU
1
0
Shift Enabled. Summation register is shifted by SHF Count bits. It takes four system clocks to execute.
ADC
1
Accumulate and Shift Enable. Values are accumulated for SUM Count times and then shifted by SHF Count.
SCNT20
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 53
SUMR0 register clears the interrupt.
SCNT2
SCNT1
SCNT0
SUMMATION COUNT
0
2
0
1
4
0
1
0
8
0
1
16
1
0
32
1
0
1
64
1
0
128
1
256
SHF20
Shift Count.
bits 20
SHF2
SHF1
SHF0
SHIFT
DIVIDE
0
1
2
0
1
2
4
0
1
0
3
8
0
1
4
16
1
0
5
32
1
0
1
6
64
1
0
7
128
1
8
256
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