參數(shù)資料
型號(hào): MSC1210Y2PAGT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 49/94頁
文件大?。?/td> 913K
代理商: MSC1210Y2PAGT
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
53
Serial Data Buffer 0 (SBUF0)
7
6
5
4
3
2
1
0
Reset Value
SFR 99h
00h
SBUF0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive
bits 70
buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls which
is enabled.
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SCK2
SCK1
SCK0
0
ORDER
MSTR
CPHA
CPOL
00h
SCK
SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
bits 75
SCK2
SCK1
SCK0
SCK PERIOD
0
tCLK/2
0
1
tCLK/4
0
1
0
tCLK/8
0
1
tCLK/16
1
0
tCLK/32
1
0
1
tCLK/64
1
0
tCLK/128
1
tCLK/256
ORDER
Set Bit Order for Transmit and Receive.
bit 3
0: Most Significant Bits First
1: Least Significant Bits First
MSTR
SPI Master Mode.
bit 2
0: Slave Mode
1: Master Mode
CPHA
Serial Clock Phase Control.
bit 1
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
CPOL
Serial Clock Polarity.
bit 0
0: SCK idle at logic LOW
1: SCK idle at logic HIGH
SPI Data Register (SPIDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Bh
00h
SPIDATA
SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are
bits 70
separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the
transmit interrupt.
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