參數(shù)資料
型號(hào)： MSC1210Y2PAGT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 28/94頁(yè)
文件大小： 913K
代理商： MSC1210Y2PAGT
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
34
ACCESSING EXTERNAL MEMORY
If external memory is used, P0 and P2 can be configured
as address and data lines. If external memory is not used,
P0 and P2 can be configured as general-purpose I/O lines
through the Hardware Configuration Register.
To enable access to external memory, bits 0 and 1 of the
HCR1 register must be set to 0. When these bits are
enabled all memory addresses for both internal and
external memory will appear on ports 0 and 2. During the
data portion of the cycle for internal memory, Port 0 will be
zero for security purposes.
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory use
signal PSEN (program store enable) as the read strobe.
Accesses to external Data Memory use RD or WR
(alternate functions of P3.7 and P3.6) to strobe the
memory.
External Program Memory and external Data Memory may
be combined if desired by applying the RD and PSEN
signals to the inputs of an AND gate and using the output
of the gate as the read strobe to the external Program/Data
Memory.
Program fetches from external Program Memory always
use a 16-bit address. Accesses to external Data Memory
can use either a 16-bit address (MOVX @DPTR) or an
8-bit address (MOVX @RI).
If Port 2 is selected for external memory use (HCR1, bit 0),
it cannot be used as general-purpose I/O. This bit (or Bit
1 of HCR1) also forces bits P3.6 and P3.7 to be used for
WR and RD instead of I/O. Port 2, P3.6, and P3.7 should
all be written to ‘1.’
If an 8-bit address is being used (MOVX @RI), the
contents of the MPAGE (92h) SFR remain at the Port 2
pins throughout the external memory cycle. This will
facilitate paging.
In any case, the low byte of the address is time-multiplexed
with the data byte on Port 0. The ADDR/DATA signals use
CMOS drivers in the Port 0, Port 2, WR, and RD output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pull-ups for
high-speed access. Signal ALE (Address Latch Enable)
should be used to capture the address byte into an external
latch. The address byte is valid at the negative transition
of ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is activated, and remains
there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at Port 0 just before the read
strobe is deactivated.
The functions of Port 0 and Port 2 are selected in Hardware
Configuration Register 1. This can only be changed during
the Flash Program mode. There is no conflict in the use of
these
registers;
they
will
either
be
used
as
general-purpose I/O or for external memory access. The
default state is for Port 0 and Port 2 to be used as
general-purpose I/O. If an external memory access is
attempted when they are configured as general-purpose
I/O, the values of Port 0 and Port 2 will not be affected.
External Program Memory is accessed under two
conditions:
1.
Whenever signal EA is LOW during reset, then all
future accesses are external; or
2.
Whenever the Program Counter (PC) contains a
number that is outside of the internal Program
Memory address range, if the ports are enabled.
If Port 0 and Port 2 are selected for external memory, all 8
bits of Port 0 and Port 2, as well as P3.6 and P3.7, are
dedicated to an output function and may not be used for
general-purpose I/O. During external program fetches,
Port 2 outputs the high byte of the PC.
Programming Flash Memory
There are four sections of Flash Memory for programming:
1.
128 configuration bytes.
2.
Reset sector (4kB) (not to be confused with the 2kB
Boot ROM).
3.
Program Memory.
4.
Data Memory.
Flash Programming Mode
There are two programming modes: parallel and serial. The
programming mode is selected by the state of the ALE and
PSEN signals during power-on reset. Serial programming
mode is selected with PSEN = 0 and ALE = 1. Parallel
programming mode is selected with PSEN = 1 and ALE = 0
(see Figure 22). If they are both HIGH, the MSC1210 will
operate in normal user mode. Both signals LOW is a
reserved mode and is not defined. Programming mode is
exited with a reset (BOR, WDT, software, or POR) and the
normal mode selected.
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