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參數(shù)資料
| 型號： | MRFIC1819 |
| 廠商： | Motorola, Inc. |
| 英文描述： | RF Power Amplifiers(RF功率放大器) |
| 中文描述： | 射頻功率放大器（射頻功率放大器） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 164K |
| 代理商： | MRFIC1819 |
MRFIC1819
8
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
APPLICATIONS INFORMATION
Design Philosophy
The MRFIC1819 is a high performance three stage GaAs
IPA (Integrated Power Amplifier) designed for DCS/PCS
handheld radios (1710–1785 MHz DCS frequency band,
1850–1910 MHz PCS frequency band). With a 3.6 V battery
supply, it delivers typically 33 dBm of Output Power with 41%
Power Added Efficiency.
It features an internal Negative Voltage Generator based
on RF rectification of the input carrier after its amplification by
two dedicated buffer stages (see Internal Block Diagram).
This method eliminates spurs found on the Output signal
when using dc/dc converter type negative voltage
generators, either on or off chip. The buffer also generates a
step–up positive voltage which can be used to drive a
N–MOS drain switch.
The RF input power is split
externally
(different from
MRFIC0919) to the 3 stage RF line–up (Q1, Q2 and Q3) and
the Buffer amplifier (Q0, QB). This arrangement allows
separate operation of Voltage Generation and Power
Amplification for maximum flexibility.
External Circuit Considerations
The MRFIC1819 can be tuned by changing the values
and/or positions of the appropriate external components (see
Figure 1: Reference Circuit). While tuning the RF line–up, it is
recommended to apply external negative supply in order to
prevent any damage to the power amplifier stages. Poor
tuning on the input may not provide enough RF power to
operate the negative voltage generator properly.
Input matching is a shunt–L, series–L high–pass structure
and should be optimized at the rated RF Input power
(e.g. 6.0 dBm). However, broadband matching is easier with
a parallel 680
resistor. This part can be removed to get
operation to a lower input power (e.g. 5.0 dBm). Since the
Input line feeds both 1st stage and buffer, Input matching
should be iterated with Buffer and Q1 drain matching. Note
that a dc blocking capacitor is included on chip.
RF input signal is fed to buffer amplifier using C12
capacitor (Figure 1). The value of this capacitor determines
the power split between RF line–up and buffer amplifier. C12
has been tuned to get the best trade–off between RF gain
and negative voltage on Pin 9.
First stage buffer amplifier is tuned with a short 80
microstrip line
which may be replaced by a chip inductor (T4
on Figure 1). Second stage buffer amplifier is supplied and
matched through a discrete chip inductor. Those two
elements are tuned to get the maximum output from voltage
generator. The overall typical buffer current is about 50 mA;
however, the negative generator needs a settling time of
2.0
μ
sec (see burst mode paragraph). During this transcient
period of time, both stages are biased to IDSS which is about
200 mA each.
The step–up positive voltage available at Pin 1 is both
decoupled and maximised by a small shunt capacitor. This
positive voltage which is approximately twice the buffer drain
voltage can be used to drive a NMOS drain switch for best
performances.
Q1 drain is supplied and matched through a printed
microstrip line that could be replaced by a discrete chip
inductor as well. Its length (or equivalent inductor value) is
tuned by sliding the RF decoupling capacitor along to get the
maximum gain on the first stage.
Q2 is supplied through a printed microstrip line that
contributes also to the interstage matching in order to provide
optimum drive to the final stage.
The line length for Q1 and Q2 is small , so replacing it with
a discrete inductor is not practical.
Q3 drain is fed via a printed line that must handle the high
supply current of that stage (2.0 Amp peak) without
significant voltage drop. This line can be buried in an inner
layer to save PCB space or be a discrete RF choke.
Output matching is accomplished with a two stages
low–pass network. Easy implementation is achieved with
shunt capacitors mounted along a 2.0 mm 30
microstrip
transmission line. Value and position are chosen to reach a
load line of 5.5
while conjugating the device output
parasitics. The network must also properly terminate the
second and third harmonic to optimize efficiency and reduce
harmonic level. Use of high Q capacitor for the first output
matching capactor circuit is recommended in order to get the
best Output Power and Efficiency performance.
NOTE: The choice of output matching capacitors type and
supplier will affect H2 and H3 level and efficiency, because
of series resonant frequency.
Biasing Considerations
The internally generated negative voltage is clamped by
an external Zener diode in order to eliminate variation linked
to Input power or Buffer supply. This negative voltage is used
by three independent bias circuits to set the proper quiescent
current of all stages. Each bias circuitry is equivalent to a
current source sinking its value from the bias pin. When the
bias pins are set to 3.0 V, nominal quiescent current and
operating point of each RF stage are selected.
Q1 and Buffer share the Bias1 (0.25 mA) while Q2 and Q3
have dedicated Bias2 (0.25 mA) and Bias3 (0.5 mA)
respectively. It is also possible to reference those bias pins to
Gnd by changing series resistors R1, R2, R3 (Figure 1) that
drops the 3.0 V.
If those pins are left opened, the corresponding stages are
pinched–off. Thus the bias pins can be used as a mean to
select the MRFIC1819 or the MRFIC0919 in a dual band
configuration. The MRFIC0919 is the partner
device to the
MRFIC1819 and is designed for GSM900 applications.
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