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參數(shù)資料
| 型號： | MR80C52XXX-36P883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 71/132頁 |
| 文件大小： | 10886K |
| 代理商： | MR80C52XXX-36P883R |
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276
8151H–AVR–02/11
ATmega128A
24.15 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description.
24.16 Register Description
24.16.1
OCDR - On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
24.16.2
MCUCSR - MCU Control and Status Register
The MCU Control and Status Register contains control bits for general MCU functions, and pro-
vides information on which reset source caused an MCU Reset.
Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit
is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the
JTAG interface, a timed sequence must be followed when changing this bit: The application soft-
ware must write this bit to the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit
7
6
5
4321
0
MSB/IDRD
LSB
OCDR
Read/Write
R/W
Initial Value
0
0000
0
Bit
7
65432
10
JTD
–
–JTRF
WDRF
BORF
EXTRF
PORF
MCUCSR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C52XXX-36SHXXX | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| MC80C32E-16SHXXX:D | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C52XXX-36SCD | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-16SHXXX | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-20/883:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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