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參數(shù)資料
| 型號： | MR80C52XXX-36P883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 132/132頁 |
| 文件大?。?/td> | 10886K |
| 代理商： | MR80C52XXX-36P883R |
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9
7593L–AVR–09/12
AT90USB64/128
2.2.8
Port E (PE7..PE0)
Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
2.2.9
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10
D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22
Ω resistor.
2.2.11
D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22
Ω resistor.
2.2.12
UGND
USB Pads Ground.
2.2.13
UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.14
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1F).
2.2.15
VBUS
USB VBUS monitor and OTG negociations.
2.2.16
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.17
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
相關(guān)PDF資料 |
PDF描述 |
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| MQ80C52XXX-36SHXXX | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| MC80C32E-16SHXXX:D | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C52XXX-36SCD | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-16SHXXX | 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-20/883:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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