參數(shù)資料
型號(hào): MR80C52XXX-36P883R
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁(yè)數(shù): 36/132頁(yè)
文件大?。?/td> 10886K
代理商: MR80C52XXX-36P883R
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203
ATmega8535(L)
2502K–AVR–10/06
Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and nega-
tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on
the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s
output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the
comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The
user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-
gram of the comparator and its surrounding logic is shown in Figure 97.
Figure 97. Analog Comparator Block Diagram(2)
Notes:
2. Refer to Figure 1 on page 2 and Table 26 on page 60 for Analog Comparator pin
placement.
Special Function IO Register –
SFIOR
Bit 3 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is
zero), the ADC multiplexer selects the negative input to the Analog Comparator. When
this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-
ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on
Analog Comparator Control
and Status Register – ACSR
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off.
This bit can be set at any time to turn off the Analog Comparator. This will reduce power
consumption in active and Idle mode. When changing the ACD bit, the Analog Compar-
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
(1)
Bit
7
6
5
4
3
2
1
0
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
SFIOR
Read/Write
R/W
R
R/W
Initial Value
0
Bit
7654
321
0
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
Initial Value
0
N/A
0
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