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| 型號(hào)： | MR80C32-25/883R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 159/182頁(yè) |
| 文件大小： | 2994K |
| 代理商： | MR80C32-25/883R |
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78
1477K–AVR–08/10
ATtiny26(L)
Watchdog
Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16
to 2048 ms. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight differ-
ent clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny26(L) resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to page 35.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control
Register for details.
Figure 43. Watchdog Timer
Watchdog Timer
Control Register –
WDTCR
Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and will always read as zero.
Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits.
Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the
Watchdog Timer function is disabled. WDE can be cleared only when the WDCE bit is set(one).
To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. A logical one must be writ-
ten to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog.
Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
Normally 1 MHz
WATCHDOG
PRESCLALER
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDE
MCU RESET
Bit
765
4
3210
$21 ($41)
–
WDCE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R/W
Initial Value
000
0
0000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C52CXXX-12SBR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C32-16SC | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-30SCD | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| MR83C154TXXX-20P883R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52XXX-25SBR | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C32-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MR80C32-36 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MR80C51BH | 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space |
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
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